TTY> CPU init (MIDR: 0x612f0280)... TTY> CPU part: 0x28 rev: 0x20 TTY> CPU: M1 Max Icestorm TTY> TTY> boot_args at 0x10003804088 TTY> revision: 2 TTY> version: 2 TTY> virt_base: 0x11f7c000 TTY> phys_base: 0x10001f7c000 TTY> mem_size: 0xfc9190000 TTY> top_of_kdata: 0x10003808000 TTY> video: TTY> base: 0x10fd1ad0000 TTY> display: 0x0 TTY> stride: 0x3600 TTY> width: 3456 TTY> height: 2234 TTY> depth: 30bpp TTY> density: 1 TTY> machine_type: 0 TTY> devtree: 0x12ffc000 TTY> devtree_size: 0x7c000 TTY> cmdline: -v TTY> boot_flags: 0x0 TTY> mem_size_act: 0x1000000000 TTY> TTY> TTY> TTY> m1n1 v1.3.1 TTY> Copyright The Asahi Linux Contributors TTY> Licensed under the MIT license TTY> TTY> Running in EL2 TTY> TTY> Device info: TTY> Model: MacBookPro18,2 TTY> Target: J316c TTY> Board-ID: 0xa TTY> Chip-ID: 0x6001 TTY> TTY> OS FW version: 13.5 (iBoot-8422.141.2) TTY> System FW version: 13.5 (iBoot-8422.141.2) TTY> Heap base: 0x10003808000 TTY> MCC: Initializing T6000 MCCs (8 instances)... TTY> MCC: Initialized T6000 MCCs (8 instances, 4 planes, 4 channels) TTY> MMU: Initializing... TTY> MMU: RAM base: 0x10000000000 TTY> MMU: Top of normal RAM: 0x10fcb10c000 TTY> MMU: Unmapping TZ0 region at 0x10fcb114000..0x10fccecc000 TTY> MMU: Unmapping TZ1 region at 0x10fcb10c000..0x10fcb114000 TTY> MMU: Unmapping TZ2 region at 0x10fda62c000..0x10fffe2c000 TTY> MMU: Adding Device-nGnRE mapping at 0x5a0000000 (0x20000000) TTY> MMU: Adding Device-nGnRE mapping at 0x5c0000000 (0x40000000) TTY> MMU: Adding Device-nGnRE mapping at 0x800000000 (0x200000000) TTY> MMU: Adding Device-nGnRE mapping at 0xa00000000 (0x80000000) TTY> MMU: Adding Device-nGnRE mapping at 0xc00000000 (0x200000000) TTY> MMU: Adding Device-nGnRE mapping at 0xe00000000 (0x80000000) TTY> MMU: Adding Device-nGnRE mapping at 0x1000000000 (0x200000000) TTY> MMU: Adding Device-nGnRE mapping at 0x1200000000 (0x80000000) TTY> MMU: Adding Device-nGnRE mapping at 0x1400000000 (0x200000000) TTY> MMU: Adding Device-nGnRE mapping at 0x1600000000 (0x80000000) TTY> MMU: Adding Normal-NC mapping at 0x10ffff40000 (0x20000) TTY> MMU: Adding Normal-NC mapping at 0x10ffff18000 (0x8000) TTY> MMU: Adding Normal-NC mapping at 0x10fffefc000 (0x4000) TTY> MMU: Adding Normal-NC mapping at 0x10fffee8000 (0x4000) TTY> MMU: Adding Normal-NC mapping at 0x10fffee4000 (0x4000) TTY> MMU: Adding Normal-NC mapping at 0x10fffed0000 (0x4000) TTY> MMU: Adding Normal-NC mapping at 0x10fffecc000 (0x4000) TTY> MMU: Adding Normal-NC mapping at 0x10fffeb8000 (0x4000) TTY> MMU: Adding Normal-NC mapping at 0x10fffeb4000 (0x4000) TTY> MMU: Adding Normal-NC mapping at 0x10fffea0000 (0x4000) TTY> MMU: Adding Normal-NC mapping at 0x10ffffb8000 (0x4000) TTY> MMU: Adding Normal-NC mapping at 0x10ffff74000 (0x4000) TTY> MMU: SCTLR_EL1: 30100180 -> 30901085 TTY> MMU: running with MMU and caches enabled! TTY> AIC: Version 2 @ 0x28e100000 TTY> AIC: AIC2 with 1/8 dies, 1806/4096 IRQs, reg_size:0c004 die_stride:04a00 TTY> AIC: Configuring 5 external interrupts TTY> WDT registers @ 0x2922b0000 TTY> WDT disabled TTY> pmgr: Cleaning up device states... TTY> pmgr: Enabling 0.ANS2, parent of active device APCIE_ST_SYS TTY> pmgr: Enabling 0.DEBUG, parent of active device DEBUG_USB TTY> pmgr: initialized, 430 devices on 1 dies found. TTY> display: Display is internal TTY> display: Display is already initialized (3456x2234) TTY> fb init: 3456x2234 (30) [s=3456] @0x10fd1ad0000 TTY> fb console: max rows 65, max cols 92 TTY> fb: display logo TTY> Initialization complete. TTY> Boot policy: sip0 = 127 TTY> Bringing up USB for early debug... TTY> i2c: want to read 1 bytes from addr 56 but can only read 0 TTY> usb: tps6598x_powerup failed for /arm-io/i2c0/hpmBusManager/hpm0. TTY> usb: failed to init hpm0 TTY> dart: dart /arm-io/dart-usb0 at 0x702f80000 is a t6000 TTY> USB0: initialized at 0x10005903c30 TTY> dart: dart /arm-io/dart-usb1 at 0xb02f80000 is a t6000 TTY> USB1: initialized at 0x10003834260 TTY> dart: dart /arm-io/dart-usb2 at 0xf02f80000 is a t6000 TTY> USB2: initialized at 0x10003834720 TTY> Waiting for proxy connection... .... Connected! Fetching ADT (0x0007C000 bytes)... Disable iodev 4 Disable iodev 5 Disable iodev 6 Disable iodev 7 Disable iodev 8 Disable iodev 9 Disable iodev 10 Initializing hypervisor over iodev 3 TTY> Starting secondary CPUs... TTY> Starting CPU 1 (0:0:1)... Started. TTY> Starting CPU 2 (0:1:0)... Started. TTY> Starting CPU 3 (0:1:1)... Started. TTY> Starting CPU 4 (0:1:2)... Started. TTY> Starting CPU 5 (0:1:3)... Started. TTY> Starting CPU 6 (0:2:0)... Started. TTY> Starting CPU 7 (0:2:1)... Started. TTY> Starting CPU 8 (0:2:2)... Started. TTY> Starting CPU 9 (0:2:3)... Started. TTY> Error getting cpu-uttdbg-reg property TTY> HV: Initializing for 42-bit PA range TTY> HV: No ECV supported Mapping MMIO range: 0x200000000 .. 0x600000000 Mapping MMIO range: 0x580000000 .. 0x700000000 Mapping MMIO range: 0x700000000 .. 0x1680000000 Removing ADT node /arm-io/dart-usb0 Removing ADT node /arm-io/atc-phy0 Removing ADT node /arm-io/usb-drd0 Removing ADT node /arm-io/acio0 Removing ADT node /arm-io/acio-cpu0 Removing ADT node /arm-io/dart-acio0 Removing ADT node /arm-io/apciec0 Removing ADT node /arm-io/dart-apciec0 Removing ADT node /arm-io/apciec0-piodma Removing ADT node /arm-io/i2c0/hpmBusManager/hpm0 Removing ADT node /arm-io/atc0-dpxbar Removing ADT node /arm-io/atc0-dpphy Removing ADT node /arm-io/atc0-dpin0 Removing ADT node /arm-io/atc0-dpin1 Removing ADT node /arm-io/atc-phy0 Total region size: 0x8f0000 bytes Physical memory: 0x10016798000 .. 0x10fcb10c000 Guest region start: 0x1001786c000 Mapping guest physical memory... Unmapping TZ carveouts... Unmap [0x10fcb114000..0x10fccecbfff] Unmap [0x10fcb10c000..0x10fcb113fff] Unmap [0x10fda62c000..0x10fffe2bfff] Loading kernel image (0x29da45 bytes)... .......................................................................................... Copying SEPFW (0x60c000 bytes)... Copying TrustCache (0x58000 bytes)... Copying preoslog (0x40000 bytes)... Adjusting addresses in ADT... Setting up bootargs at 0x10018158000... Setting secondary CPU RVBARs... cpu1: [0x210150000] = 0x1001786c000 cpu2: [0x211050000] = 0x1001786c000 cpu3: [0x211150000] = 0x1001786c000 cpu4: [0x211250000] = 0x1001786c000 cpu5: [0x211350000] = 0x1001786c000 cpu6: [0x212050000] = 0x1001786c000 cpu7: [0x212150000] = 0x1001786c000 cpu8: [0x212250000] = 0x1001786c000 cpu9: [0x212350000] = 0x1001786c000 Disabling other iodevs... - 0 - 1 - 2 - 4 - 5 - 6 - 7 - 8 - 9 - 10 Doing essential MMIO remaps... Updating page tables... PT[200000000:23d29c044] -> HW:HW PT[23d29c044:23d29c048] -> RESERVED PMGR HACK PT[23d29c048:23d29c05c] -> HW:HW PT[23d29c05c:23d29c060] -> RESERVED PMGR HACK PT[23d29c060:28e0801d8] -> HW:HW PT[28e0801d8:28e0801dc] -> RESERVED PMGR HACK PT[28e0801dc:28e0801f0] -> HW:HW PT[28e0801f0:28e0801f4] -> RESERVED PMGR HACK PT[28e0801f4:28e080200] -> HW:HW PT[28e080200:28e080204] -> RESERVED PMGR HACK PT[28e080204:28e080218] -> HW:HW PT[28e080218:28e08021c] -> RESERVED PMGR HACK PT[28e08021c:28e080238] -> HW:HW PT[28e080238:28e08023c] -> RESERVED PMGR HACK PT[28e08023c:28e0d4000] -> HW:HW PT[28e0d4000:28e0d4020] -> RESERVED CPU_START PT[28e0d4020:28e100000] -> HW:HW PT[28e100000:28e150000] -> RESERVED AIC_IRQ PT[28e150000:28e580148] -> HW:HW PT[28e580148:28e58014c] -> RESERVED PMGR HACK PT[28e58014c:28e580150] -> HW:HW PT[28e580150:28e580154] -> RESERVED PMGR HACK PT[28e580154:28e580160] -> HW:HW PT[28e580160:28e580164] -> RESERVED PMGR HACK PT[28e580164:28e580180] -> HW:HW PT[28e580180:28e580184] -> RESERVED PMGR HACK PT[28e580184:28e580230] -> HW:HW PT[28e580230:28e580234] -> RESERVED PMGR HACK PT[28e580234:28e580240] -> HW:HW PT[28e580240:28e580244] -> RESERVED PMGR HACK PT[28e580244:28e584000] -> HW:HW PT[28e584000:28e584100] -> SYNC.RW PrintTracer PT[28e584100:292280088] -> HW:HW PT[292280088:29228008c] -> RESERVED PMGR HACK PT[29228008c:2922800d0] -> HW:HW PT[2922800d0:2922800d4] -> RESERVED PMGR HACK PT[2922800d4:384000000] -> HW:HW PT[384000000:3860e8000] -> SYNC.RW PrintTracer PT[3860e8000:3860ec000] -> SYNC.RW PrintTracer PT[3860ec000:3860f0000] -> SYNC.RW PrintTracer PT[3860f0000:3860f4000] -> SYNC.RW PrintTracer PT[3860f4000:3860f8000] -> SYNC.RW PrintTracer PT[3860f8000:3860fc000] -> SYNC.RW PrintTracer PT[3860fc000:386100000] -> SYNC.RW PrintTracer PT[386100000:388000000] -> SYNC.RW PrintTracer PT[388000000:39b200000] -> HW:HW PT[39b200000:39b204000] -> RESERVED VUART PT[39b204000:1680000000] -> HW:HW PT[10000000000:10001f7c000] -> HW:RAM-LOW PT[10016798000:10fcb10c000] -> HW:RAM-HIGH PT[10fcb10c000:10fccecc000] -> *UNMAPPED* PT[10fccecc000:10fda62c000] -> HW:RAM-HIGH PT[10fda62c000:10fffe2c000] -> *UNMAPPED* PT[10fffe2c000:11000000000] -> HW:RAM-HIGH Uploading ADT (0x70ba0 bytes)... Improving logo... Shutting down framebuffer... Enabling SPRR... Enabling GXF... Jumping to entrypoint at 0x1001786c800 [cpu0] Pass: msr OSLAR_EL1, x0 = 0 (OK) (OSLAR_EL1) [cpu0] Pass: mrs x0, HID5_EL1 = 2082df50f700df12 (HID5_EL1) [cpu0] Pass: msr HID5_EL1, x0 = 2082df50f700df12 (OK) (HID5_EL1) [cpu0] Pass: mrs x0, EHID9_EL1 = 600000811 (EHID9_EL1) [cpu0] Pass: msr EHID9_EL1, x0 = 600000811 (OK) (EHID9_EL1) [cpu0] Pass: mrs x0, EHID10_EL1 = 3000528002788 (EHID10_EL1) [cpu0] Pass: msr EHID10_EL1, x0 = 3000528002788 (OK) (EHID10_EL1) [cpu0] Pass: mrs x0, EHID20_EL1 = 618000 (EHID20_EL1) [cpu0] Pass: msr EHID20_EL1, x0 = 618000 (OK) (EHID20_EL1) [cpu0] Pass: mrs x0, EHID20_EL1 = 618000 (EHID20_EL1) [cpu0] Pass: msr EHID20_EL1, x0 = 618000 (OK) (EHID20_EL1) [cpu0] Pass: mrs x0, EHID20_EL1 = 618000 (EHID20_EL1) [cpu0] Pass: msr EHID20_EL1, x0 = 618000 (OK) (EHID20_EL1) [cpu0] Pass: mrs x1, ACC_CFG_EL1 = d (ACC_CFG_EL1) [cpu0] Skip: msr ACC_CFG_EL1, x1 = d [cpu0] PMGR R 28e580180+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e0801d8+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e0801f0+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e0801d8+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e0801d8+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e080200+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e0801f0+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e080200+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e080218+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e080200+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e080200+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e080238+0:32 = 0xff -> 0xff [cpu0] PMGR R 28e080218+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e080218+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e0801d8+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e0801d8+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e080218+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e080218+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e580148+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e0801d8+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e580150+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e580148+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e580150+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e580160+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e580150+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e580180+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e580160+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e580180+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e580180+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e580180+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e580180+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e580180+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e580180+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e580180+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e580180+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e580180+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e580180+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e580180+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e580180+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e580180+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e580180+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e580180+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e580180+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e580230+0:32 = 0xff -> 0xff [cpu0] PMGR R 28e580180+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e580230+0:32 = 0xff -> 0xff [cpu0] PMGR R 28e580240+0:32 = 0xff -> 0xff [cpu0] PMGR R 28e580230+0:32 = 0xff -> 0xff [cpu0] PMGR R 28e580230+0:32 = 0xff -> 0xff [cpu0] PMGR R 28e580160+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e0801d8+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e0801d8+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 292280088+0:32 = 0xff -> 0xff [cpu0] PMGR R 2922800d0+0:32 = 0xff -> 0xff [cpu0] PMGR R 292280088+0:32 = 0xff -> 0xff [cpu0] PMGR R 28e080238+0:32 = 0xff -> 0xff [cpu0] CPUSTART W 28e0d4000+4:32 = 0x2 [cpu0] CPUSTART W 28e0d4000+8:32 = 0x2 [cpu0] Starting guest secondary 0:0:1 [cpu0] CPU #1: RVBAR = 0x1001786c000 TTY> HV: Initializing secondary 1 TTY> HV: Entering guest secondary 1 at 0x1001786c000 [cpu0] PT[23d29c044:23d29c048] -> RESERVED PMGR HACK [cpu0] PT[23d29c048:23d29c04c] -> RESERVED CPU STATE HACK [cpu1] Pass: msr OSLAR_EL1, x0 = 0 (OK) (OSLAR_EL1) [cpu1] Pass: mrs x0, HID5_EL1 = 2082df50f700df12 (HID5_EL1) [cpu1] Pass: msr HID5_EL1, x0 = 2082df50f700df12 (OK) (HID5_EL1) [cpu1] Pass: mrs x0, EHID9_EL1 = 600000811 (EHID9_EL1) [cpu1] Pass: msr EHID9_EL1, x0 = 600000811 (OK) (EHID9_EL1) [cpu1] Pass: mrs x0, EHID10_EL1 = 3000528002788 (EHID10_EL1) [cpu1] Pass: msr EHID10_EL1, x0 = 3000528002788 (OK) (EHID10_EL1) [cpu1] Pass: mrs x0, EHID20_EL1 = 618000 (EHID20_EL1) [cpu1] Pass: msr EHID20_EL1, x0 = 618000 (OK) (EHID20_EL1) [cpu1] Pass: mrs x0, EHID20_EL1 = 618000 (EHID20_EL1) [cpu1] Pass: msr EHID20_EL1, x0 = 618000 (OK) (EHID20_EL1) [cpu1] Pass: mrs x0, EHID20_EL1 = 618000 (EHID20_EL1) [cpu1] Pass: msr EHID20_EL1, x0 = 618000 (OK) (EHID20_EL1) [cpu1] Pass: mrs x1, ACC_CFG_EL1 = d (ACC_CFG_EL1) [cpu1] Skip: msr ACC_CFG_EL1, x1 = d [cpu0] CPUSTART W 28e0d4000+4:32 = 0x10 [cpu0] CPUSTART W 28e0d4000+c:32 = 0x1 [cpu0] Starting guest secondary 0:1:0 [cpu0] CPU #2: RVBAR = 0x1001786c000 TTY> HV: Initializing secondary 2 TTY> HV: Entering guest secondary 2 at 0x1001786c000 [cpu0] PT[23d29c044:23d29c048] -> RESERVED PMGR HACK [cpu0] PT[23d29c048:23d29c04c] -> RESERVED CPU STATE HACK [cpu2] Pass: msr OSLAR_EL1, x0 = 0 (OK) (OSLAR_EL1) [cpu2] Pass: mrs x0, HID13_EL1 = c332200211010205 (HID13_EL1) [cpu2] Pass: msr HID13_EL1, x0 = c332200211010205 (OK) (HID13_EL1) [cpu2] Pass: mrs x0, HID14_EL1 = 500000bb8 (HID14_EL1) [cpu2] Pass: msr HID14_EL1, x0 = 500000bb8 (OK) (HID14_EL1) [cpu2] Pass: mrs x0, HID0_EL1 = 10002990120e0e00 (HID0_EL1) [cpu2] Pass: msr HID0_EL1, x0 = 10002990120e0e00 (OK) (HID0_EL1) [cpu2] Pass: mrs x0, HID1_EL1 = 1400000002000000 (HID1_EL1) [cpu2] Pass: msr HID1_EL1, x0 = 1400000002000000 (OK) (HID1_EL1) [cpu2] Pass: mrs x0, HID3_EL1 = 4180000cf8001fe0 (HID3_EL1) [cpu2] Pass: msr HID3_EL1, x0 = 4180000cf8001fe0 (OK) (HID3_EL1) [cpu2] Pass: mrs x0, HID5_EL1 = 2082df205700ff12 (HID5_EL1) [cpu2] Pass: msr HID5_EL1, x0 = 2082df205700ff12 (OK) (HID5_EL1) [cpu2] Pass: mrs x0, HID9_EL1 = 8100086c000000 (HID9_EL1) [cpu2] Pass: msr HID9_EL1, x0 = 8100086c000000 (OK) (HID9_EL1) [cpu2] Pass: mrs x0, HID11_EL1 = 804000010008000 (HID11_EL1) [cpu2] Pass: msr HID11_EL1, x0 = 804000010008000 (OK) (HID11_EL1) [cpu2] Pass: mrs x0, HID13_EL1 = c332200211010205 (HID13_EL1) [cpu2] Pass: msr HID13_EL1, x0 = c332200211010205 (OK) (HID13_EL1) [cpu2] Pass: mrs x0, HID16_EL1 = 6900000440000000 (HID16_EL1) [cpu2] Pass: msr HID16_EL1, x0 = 6900000440000000 (OK) (HID16_EL1) [cpu2] Pass: mrs x0, HID0_EL1 = 10002990120e0e00 (HID0_EL1) [cpu2] Pass: msr HID0_EL1, x0 = 10002990120e0e00 (OK) (HID0_EL1) [cpu2] Pass: mrs x0, HID7_EL1 = 3110000 (HID7_EL1) [cpu2] Pass: msr HID7_EL1, x0 = 3110000 (OK) (HID7_EL1) [cpu2] Pass: mrs x0, HID7_EL1 = 3110000 (HID7_EL1) [cpu2] Pass: msr HID7_EL1, x0 = 3110000 (OK) (HID7_EL1) [cpu2] Pass: mrs x0, HID9_EL1 = 8100086c000000 (HID9_EL1) [cpu2] Pass: msr HID9_EL1, x0 = 8100086c000000 (OK) (HID9_EL1) [cpu2] Pass: mrs x0, HID18_EL1 = 2000040004000 (HID18_EL1) [cpu2] Pass: msr HID18_EL1, x0 = 2000040004000 (OK) (HID18_EL1) [cpu2] Pass: mrs x0, HID21_EL1 = 1040000 (HID21_EL1) [cpu2] Pass: msr HID21_EL1, x0 = 1040000 (OK) (HID21_EL1) [cpu2] Pass: mrs x0, HID1_EL1 = 1400000002000000 (HID1_EL1) [cpu2] Pass: msr HID1_EL1, x0 = 1400000002000000 (OK) (HID1_EL1) [cpu2] Pass: mrs x0, HID9_EL1 = 8100086c000000 (HID9_EL1) [cpu2] Pass: msr HID9_EL1, x0 = 8100086c000000 (OK) (HID9_EL1) [cpu2] Pass: mrs x0, HID11_EL1 = 804000010008000 (HID11_EL1) [cpu2] Pass: msr HID11_EL1, x0 = 804000010008000 (OK) (HID11_EL1) [cpu2] Pass: mrs x0, HID1_EL1 = 1400000002000000 (HID1_EL1) [cpu2] Pass: msr HID1_EL1, x0 = 1400000002000000 (OK) (HID1_EL1) [cpu2] Pass: mrs x0, HID18_EL1 = 2000040004000 (HID18_EL1) [cpu2] Pass: msr HID18_EL1, x0 = 2000040004000 (OK) (HID18_EL1) [cpu2] Pass: mrs x1, ACC_CFG_EL1 = d (ACC_CFG_EL1) [cpu2] Skip: msr ACC_CFG_EL1, x1 = d [cpu0] CPUSTART W 28e0d4000+4:32 = 0x20 [cpu0] CPUSTART W 28e0d4000+c:32 = 0x2 [cpu0] Starting guest secondary 0:1:1 [cpu0] CPU #3: RVBAR = 0x1001786c000 TTY> HV: Initializing secondary 3 TTY> HV: Entering guest secondary 3 at 0x1001786c000 [cpu0] PT[23d29c044:23d29c048] -> RESERVED PMGR HACK [cpu0] PT[23d29c048:23d29c04c] -> RESERVED CPU STATE HACK [cpu3] Pass: msr OSLAR_EL1, x0 = 0 (OK) (OSLAR_EL1) [cpu3] Pass: mrs x0, HID13_EL1 = c332200211010205 (HID13_EL1) [cpu3] Pass: msr HID13_EL1, x0 = c332200211010205 (OK) (HID13_EL1) [cpu3] Pass: mrs x0, HID14_EL1 = 500000bb8 (HID14_EL1) [cpu3] Pass: msr HID14_EL1, x0 = 500000bb8 (OK) (HID14_EL1) [cpu3] Pass: mrs x0, HID0_EL1 = 10002990120e0e00 (HID0_EL1) [cpu3] Pass: msr HID0_EL1, x0 = 10002990120e0e00 (OK) (HID0_EL1) [cpu3] Pass: mrs x0, HID1_EL1 = 1400000002000000 (HID1_EL1) [cpu3] Pass: msr HID1_EL1, x0 = 1400000002000000 (OK) (HID1_EL1) [cpu3] Pass: mrs x0, HID3_EL1 = 4180000cf8001fe0 (HID3_EL1) [cpu3] Pass: msr HID3_EL1, x0 = 4180000cf8001fe0 (OK) (HID3_EL1) [cpu3] Pass: mrs x0, HID5_EL1 = 2082df205700ff12 (HID5_EL1) [cpu3] Pass: msr HID5_EL1, x0 = 2082df205700ff12 (OK) (HID5_EL1) [cpu3] Pass: mrs x0, HID9_EL1 = 8100086c000000 (HID9_EL1) [cpu3] Pass: msr HID9_EL1, x0 = 8100086c000000 (OK) (HID9_EL1) [cpu3] Pass: mrs x0, HID11_EL1 = 804000010008000 (HID11_EL1) [cpu3] Pass: msr HID11_EL1, x0 = 804000010008000 (OK) (HID11_EL1) [cpu3] Pass: mrs x0, HID13_EL1 = c332200211010205 (HID13_EL1) [cpu3] Pass: msr HID13_EL1, x0 = c332200211010205 (OK) (HID13_EL1) [cpu3] Pass: mrs x0, HID16_EL1 = 6900000440000000 (HID16_EL1) [cpu3] Pass: msr HID16_EL1, x0 = 6900000440000000 (OK) (HID16_EL1) [cpu3] Pass: mrs x0, HID0_EL1 = 10002990120e0e00 (HID0_EL1) [cpu3] Pass: msr HID0_EL1, x0 = 10002990120e0e00 (OK) (HID0_EL1) [cpu3] Pass: mrs x0, HID7_EL1 = 3110000 (HID7_EL1) [cpu3] Pass: msr HID7_EL1, x0 = 3110000 (OK) (HID7_EL1) [cpu3] Pass: mrs x0, HID7_EL1 = 3110000 (HID7_EL1) [cpu3] Pass: msr HID7_EL1, x0 = 3110000 (OK) (HID7_EL1) [cpu3] Pass: mrs x0, HID9_EL1 = 8100086c000000 (HID9_EL1) [cpu3] Pass: msr HID9_EL1, x0 = 8100086c000000 (OK) (HID9_EL1) [cpu3] Pass: mrs x0, HID18_EL1 = 2000040004000 (HID18_EL1) [cpu3] Pass: msr HID18_EL1, x0 = 2000040004000 (OK) (HID18_EL1) [cpu3] Pass: mrs x0, HID21_EL1 = 1040000 (HID21_EL1) [cpu3] Pass: msr HID21_EL1, x0 = 1040000 (OK) (HID21_EL1) [cpu3] Pass: mrs x0, HID1_EL1 = 1400000002000000 (HID1_EL1) [cpu3] Pass: msr HID1_EL1, x0 = 1400000002000000 (OK) (HID1_EL1) [cpu3] Pass: mrs x0, HID9_EL1 = 8100086c000000 (HID9_EL1) [cpu3] Pass: msr HID9_EL1, x0 = 8100086c000000 (OK) (HID9_EL1) [cpu3] Pass: mrs x0, HID11_EL1 = 804000010008000 (HID11_EL1) [cpu3] Pass: msr HID11_EL1, x0 = 804000010008000 (OK) (HID11_EL1) [cpu3] Pass: mrs x0, HID1_EL1 = 1400000002000000 (HID1_EL1) [cpu3] Pass: msr HID1_EL1, x0 = 1400000002000000 (OK) (HID1_EL1) [cpu3] Pass: mrs x0, HID18_EL1 = 2000040004000 (HID18_EL1) [cpu3] Pass: msr HID18_EL1, x0 = 2000040004000 (OK) (HID18_EL1) [cpu3] Pass: mrs x1, ACC_CFG_EL1 = d (ACC_CFG_EL1) [cpu3] Skip: msr ACC_CFG_EL1, x1 = d [cpu0] CPUSTART W 28e0d4000+4:32 = 0x40 [cpu0] CPUSTART W 28e0d4000+c:32 = 0x4 [cpu0] Starting guest secondary 0:1:2 [cpu0] CPU #4: RVBAR = 0x1001786c000 TTY> HV: Initializing secondary 4 TTY> HV: Entering guest secondary 4 at 0x1001786c000 [cpu0] PT[23d29c044:23d29c048] -> RESERVED PMGR HACK [cpu0] PT[23d29c048:23d29c04c] -> RESERVED CPU STATE HACK [cpu4] Pass: msr OSLAR_EL1, x0 = 0 (OK) (OSLAR_EL1) [cpu4] Pass: mrs x0, HID13_EL1 = c332200211010205 (HID13_EL1) [cpu4] Pass: msr HID13_EL1, x0 = c332200211010205 (OK) (HID13_EL1) [cpu4] Pass: mrs x0, HID14_EL1 = 500000bb8 (HID14_EL1) [cpu4] Pass: msr HID14_EL1, x0 = 500000bb8 (OK) (HID14_EL1) [cpu4] Pass: mrs x0, HID0_EL1 = 10002990120e0e00 (HID0_EL1) [cpu4] Pass: msr HID0_EL1, x0 = 10002990120e0e00 (OK) (HID0_EL1) [cpu4] Pass: mrs x0, HID1_EL1 = 1400000002000000 (HID1_EL1) [cpu4] Pass: msr HID1_EL1, x0 = 1400000002000000 (OK) (HID1_EL1) [cpu4] Pass: mrs x0, HID3_EL1 = 4180000cf8001fe0 (HID3_EL1) [cpu4] Pass: msr HID3_EL1, x0 = 4180000cf8001fe0 (OK) (HID3_EL1) [cpu4] Pass: mrs x0, HID5_EL1 = 2082df205700ff12 (HID5_EL1) [cpu4] Pass: msr HID5_EL1, x0 = 2082df205700ff12 (OK) (HID5_EL1) [cpu4] Pass: mrs x0, HID9_EL1 = 8100086c000000 (HID9_EL1) [cpu4] Pass: msr HID9_EL1, x0 = 8100086c000000 (OK) (HID9_EL1) [cpu4] Pass: mrs x0, HID11_EL1 = 804000010008000 (HID11_EL1) [cpu4] Pass: msr HID11_EL1, x0 = 804000010008000 (OK) (HID11_EL1) [cpu4] Pass: mrs x0, HID13_EL1 = c332200211010205 (HID13_EL1) [cpu4] Pass: msr HID13_EL1, x0 = c332200211010205 (OK) (HID13_EL1) [cpu4] Pass: mrs x0, HID16_EL1 = 6900000440000000 (HID16_EL1) [cpu4] Pass: msr HID16_EL1, x0 = 6900000440000000 (OK) (HID16_EL1) [cpu4] Pass: mrs x0, HID0_EL1 = 10002990120e0e00 (HID0_EL1) [cpu4] Pass: msr HID0_EL1, x0 = 10002990120e0e00 (OK) (HID0_EL1) [cpu4] Pass: mrs x0, HID7_EL1 = 3110000 (HID7_EL1) [cpu4] Pass: msr HID7_EL1, x0 = 3110000 (OK) (HID7_EL1) [cpu4] Pass: mrs x0, HID7_EL1 = 3110000 (HID7_EL1) [cpu4] Pass: msr HID7_EL1, x0 = 3110000 (OK) (HID7_EL1) [cpu4] Pass: mrs x0, HID9_EL1 = 8100086c000000 (HID9_EL1) [cpu4] Pass: msr HID9_EL1, x0 = 8100086c000000 (OK) (HID9_EL1) [cpu4] Pass: mrs x0, HID18_EL1 = 2000040004000 (HID18_EL1) [cpu4] Pass: msr HID18_EL1, x0 = 2000040004000 (OK) (HID18_EL1) [cpu4] Pass: mrs x0, HID21_EL1 = 1040000 (HID21_EL1) [cpu4] Pass: msr HID21_EL1, x0 = 1040000 (OK) (HID21_EL1) [cpu4] Pass: mrs x0, HID1_EL1 = 1400000002000000 (HID1_EL1) [cpu4] Pass: msr HID1_EL1, x0 = 1400000002000000 (OK) (HID1_EL1) [cpu4] Pass: mrs x0, HID9_EL1 = 8100086c000000 (HID9_EL1) [cpu4] Pass: msr HID9_EL1, x0 = 8100086c000000 (OK) (HID9_EL1) [cpu4] Pass: mrs x0, HID11_EL1 = 804000010008000 (HID11_EL1) [cpu4] Pass: msr HID11_EL1, x0 = 804000010008000 (OK) (HID11_EL1) [cpu4] Pass: mrs x0, HID1_EL1 = 1400000002000000 (HID1_EL1) [cpu4] Pass: msr HID1_EL1, x0 = 1400000002000000 (OK) (HID1_EL1) [cpu4] Pass: mrs x0, HID18_EL1 = 2000040004000 (HID18_EL1) [cpu4] Pass: msr HID18_EL1, x0 = 2000040004000 (OK) (HID18_EL1) [cpu4] Pass: mrs x1, ACC_CFG_EL1 = d (ACC_CFG_EL1) [cpu4] Skip: msr ACC_CFG_EL1, x1 = d [cpu0] CPUSTART W 28e0d4000+4:32 = 0x80 [cpu0] CPUSTART W 28e0d4000+c:32 = 0x8 [cpu0] Starting guest secondary 0:1:3 [cpu0] CPU #5: RVBAR = 0x1001786c000 TTY> HV: Initializing secondary 5 TTY> HV: Entering guest secondary 5 at 0x1001786c000 [cpu0] PT[23d29c044:23d29c048] -> RESERVED PMGR HACK [cpu0] PT[23d29c048:23d29c04c] -> RESERVED CPU STATE HACK [cpu5] Pass: msr OSLAR_EL1, x0 = 0 (OK) (OSLAR_EL1) [cpu5] Pass: mrs x0, HID13_EL1 = c332200211010205 (HID13_EL1) [cpu5] Pass: msr HID13_EL1, x0 = c332200211010205 (OK) (HID13_EL1) [cpu5] Pass: mrs x0, HID14_EL1 = 500000bb8 (HID14_EL1) [cpu5] Pass: msr HID14_EL1, x0 = 500000bb8 (OK) (HID14_EL1) [cpu5] Pass: mrs x0, HID0_EL1 = 10002990120e0e00 (HID0_EL1) [cpu5] Pass: msr HID0_EL1, x0 = 10002990120e0e00 (OK) (HID0_EL1) [cpu5] Pass: mrs x0, HID1_EL1 = 1400000002000000 (HID1_EL1) [cpu5] Pass: msr HID1_EL1, x0 = 1400000002000000 (OK) (HID1_EL1) [cpu5] Pass: mrs x0, HID3_EL1 = 4180000cf8001fe0 (HID3_EL1) [cpu5] Pass: msr HID3_EL1, x0 = 4180000cf8001fe0 (OK) (HID3_EL1) [cpu5] Pass: mrs x0, HID5_EL1 = 2082df205700ff12 (HID5_EL1) [cpu5] Pass: msr HID5_EL1, x0 = 2082df205700ff12 (OK) (HID5_EL1) [cpu5] Pass: mrs x0, HID9_EL1 = 8100086c000000 (HID9_EL1) [cpu5] Pass: msr HID9_EL1, x0 = 8100086c000000 (OK) (HID9_EL1) [cpu5] Pass: mrs x0, HID11_EL1 = 804000010008000 (HID11_EL1) [cpu5] Pass: msr HID11_EL1, x0 = 804000010008000 (OK) (HID11_EL1) [cpu5] Pass: mrs x0, HID13_EL1 = c332200211010205 (HID13_EL1) [cpu5] Pass: msr HID13_EL1, x0 = c332200211010205 (OK) (HID13_EL1) [cpu5] Pass: mrs x0, HID16_EL1 = 6900000440000000 (HID16_EL1) [cpu5] Pass: msr HID16_EL1, x0 = 6900000440000000 (OK) (HID16_EL1) [cpu5] Pass: mrs x0, HID0_EL1 = 10002990120e0e00 (HID0_EL1) [cpu5] Pass: msr HID0_EL1, x0 = 10002990120e0e00 (OK) (HID0_EL1) [cpu5] Pass: mrs x0, HID7_EL1 = 3110000 (HID7_EL1) [cpu5] Pass: msr HID7_EL1, x0 = 3110000 (OK) (HID7_EL1) [cpu5] Pass: mrs x0, HID7_EL1 = 3110000 (HID7_EL1) [cpu5] Pass: msr HID7_EL1, x0 = 3110000 (OK) (HID7_EL1) [cpu5] Pass: mrs x0, HID9_EL1 = 8100086c000000 (HID9_EL1) [cpu5] Pass: msr HID9_EL1, x0 = 8100086c000000 (OK) (HID9_EL1) [cpu5] Pass: mrs x0, HID18_EL1 = 2000040004000 (HID18_EL1) [cpu5] Pass: msr HID18_EL1, x0 = 2000040004000 (OK) (HID18_EL1) [cpu5] Pass: mrs x0, HID21_EL1 = 1040000 (HID21_EL1) [cpu5] Pass: msr HID21_EL1, x0 = 1040000 (OK) (HID21_EL1) [cpu5] Pass: mrs x0, HID1_EL1 = 1400000002000000 (HID1_EL1) [cpu5] Pass: msr HID1_EL1, x0 = 1400000002000000 (OK) (HID1_EL1) [cpu5] Pass: mrs x0, HID9_EL1 = 8100086c000000 (HID9_EL1) [cpu5] Pass: msr HID9_EL1, x0 = 8100086c000000 (OK) (HID9_EL1) [cpu5] Pass: mrs x0, HID11_EL1 = 804000010008000 (HID11_EL1) [cpu5] Pass: msr HID11_EL1, x0 = 804000010008000 (OK) (HID11_EL1) [cpu5] Pass: mrs x0, HID1_EL1 = 1400000002000000 (HID1_EL1) [cpu5] Pass: msr HID1_EL1, x0 = 1400000002000000 (OK) (HID1_EL1) [cpu5] Pass: mrs x0, HID18_EL1 = 2000040004000 (HID18_EL1) [cpu5] Pass: msr HID18_EL1, x0 = 2000040004000 (OK) (HID18_EL1) [cpu5] Pass: mrs x1, ACC_CFG_EL1 = d (ACC_CFG_EL1) [cpu5] Skip: msr ACC_CFG_EL1, x1 = d [cpu0] CPUSTART W 28e0d4000+4:32 = 0x100 [cpu0] CPUSTART W 28e0d4000+10:32 = 0x1 [cpu0] Starting guest secondary 0:2:0 [cpu0] CPU #6: RVBAR = 0x1001786c000 TTY> HV: Initializing secondary 6 TTY> HV: Entering guest secondary 6 at 0x1001786c000 [cpu0] PT[23d29c044:23d29c048] -> RESERVED PMGR HACK [cpu0] PT[23d29c048:23d29c04c] -> RESERVED CPU STATE HACK [cpu6] Pass: msr OSLAR_EL1, x0 = 0 (OK) (OSLAR_EL1) [cpu6] Pass: mrs x0, HID13_EL1 = c332200211010205 (HID13_EL1) [cpu6] Pass: msr HID13_EL1, x0 = c332200211010205 (OK) (HID13_EL1) [cpu6] Pass: mrs x0, HID14_EL1 = 500000bb8 (HID14_EL1) [cpu6] Pass: msr HID14_EL1, x0 = 500000bb8 (OK) (HID14_EL1) [cpu6] Pass: mrs x0, HID0_EL1 = 10002990120e0e00 (HID0_EL1) [cpu6] Pass: msr HID0_EL1, x0 = 10002990120e0e00 (OK) (HID0_EL1) [cpu6] Pass: mrs x0, HID1_EL1 = 1400000002000000 (HID1_EL1) [cpu6] Pass: msr HID1_EL1, x0 = 1400000002000000 (OK) (HID1_EL1) [cpu6] Pass: mrs x0, HID3_EL1 = 4180000cf8001fe0 (HID3_EL1) [cpu6] Pass: msr HID3_EL1, x0 = 4180000cf8001fe0 (OK) (HID3_EL1) [cpu6] Pass: mrs x0, HID5_EL1 = 2082df205700ff12 (HID5_EL1) [cpu6] Pass: msr HID5_EL1, x0 = 2082df205700ff12 (OK) (HID5_EL1) [cpu6] Pass: mrs x0, HID9_EL1 = 8100086c000000 (HID9_EL1) [cpu6] Pass: msr HID9_EL1, x0 = 8100086c000000 (OK) (HID9_EL1) [cpu6] Pass: mrs x0, HID11_EL1 = 804000010008000 (HID11_EL1) [cpu6] Pass: msr HID11_EL1, x0 = 804000010008000 (OK) (HID11_EL1) [cpu6] Pass: mrs x0, HID13_EL1 = c332200211010205 (HID13_EL1) [cpu6] Pass: msr HID13_EL1, x0 = c332200211010205 (OK) (HID13_EL1) [cpu6] Pass: mrs x0, HID16_EL1 = 6900000440000000 (HID16_EL1) [cpu6] Pass: msr HID16_EL1, x0 = 6900000440000000 (OK) (HID16_EL1) [cpu6] Pass: mrs x0, HID0_EL1 = 10002990120e0e00 (HID0_EL1) [cpu6] Pass: msr HID0_EL1, x0 = 10002990120e0e00 (OK) (HID0_EL1) [cpu6] Pass: mrs x0, HID7_EL1 = 3110000 (HID7_EL1) [cpu6] Pass: msr HID7_EL1, x0 = 3110000 (OK) (HID7_EL1) [cpu6] Pass: mrs x0, HID7_EL1 = 3110000 (HID7_EL1) [cpu6] Pass: msr HID7_EL1, x0 = 3110000 (OK) (HID7_EL1) [cpu6] Pass: mrs x0, HID9_EL1 = 8100086c000000 (HID9_EL1) [cpu6] Pass: msr HID9_EL1, x0 = 8100086c000000 (OK) (HID9_EL1) [cpu6] Pass: mrs x0, HID18_EL1 = 2000040004000 (HID18_EL1) [cpu6] Pass: msr HID18_EL1, x0 = 2000040004000 (OK) (HID18_EL1) [cpu6] Pass: mrs x0, HID21_EL1 = 1040000 (HID21_EL1) [cpu6] Pass: msr HID21_EL1, x0 = 1040000 (OK) (HID21_EL1) [cpu6] Pass: mrs x0, HID1_EL1 = 1400000002000000 (HID1_EL1) [cpu6] Pass: msr HID1_EL1, x0 = 1400000002000000 (OK) (HID1_EL1) [cpu6] Pass: mrs x0, HID9_EL1 = 8100086c000000 (HID9_EL1) [cpu6] Pass: msr HID9_EL1, x0 = 8100086c000000 (OK) (HID9_EL1) [cpu6] Pass: mrs x0, HID11_EL1 = 804000010008000 (HID11_EL1) [cpu6] Pass: msr HID11_EL1, x0 = 804000010008000 (OK) (HID11_EL1) [cpu6] Pass: mrs x0, HID1_EL1 = 1400000002000000 (HID1_EL1) [cpu6] Pass: msr HID1_EL1, x0 = 1400000002000000 (OK) (HID1_EL1) [cpu6] Pass: mrs x0, HID18_EL1 = 2000040004000 (HID18_EL1) [cpu6] Pass: msr HID18_EL1, x0 = 2000040004000 (OK) (HID18_EL1) [cpu6] Pass: mrs x1, ACC_CFG_EL1 = d (ACC_CFG_EL1) [cpu6] Skip: msr ACC_CFG_EL1, x1 = d [cpu0] CPUSTART W 28e0d4000+4:32 = 0x200 [cpu0] CPUSTART W 28e0d4000+10:32 = 0x2 [cpu0] Starting guest secondary 0:2:1 [cpu0] CPU #7: RVBAR = 0x1001786c000 TTY> HV: Initializing secondary 7 TTY> HV: Entering guest secondary 7 at 0x1001786c000 [cpu0] PT[23d29c044:23d29c048] -> RESERVED PMGR HACK [cpu0] PT[23d29c048:23d29c04c] -> RESERVED CPU STATE HACK [cpu7] Pass: msr OSLAR_EL1, x0 = 0 (OK) (OSLAR_EL1) [cpu7] Pass: mrs x0, HID13_EL1 = c332200211010205 (HID13_EL1) [cpu7] Pass: msr HID13_EL1, x0 = c332200211010205 (OK) (HID13_EL1) [cpu7] Pass: mrs x0, HID14_EL1 = 500000bb8 (HID14_EL1) [cpu7] Pass: msr HID14_EL1, x0 = 500000bb8 (OK) (HID14_EL1) [cpu7] Pass: mrs x0, HID0_EL1 = 10002990120e0e00 (HID0_EL1) [cpu7] Pass: msr HID0_EL1, x0 = 10002990120e0e00 (OK) (HID0_EL1) [cpu7] Pass: mrs x0, HID1_EL1 = 1400000002000000 (HID1_EL1) [cpu7] Pass: msr HID1_EL1, x0 = 1400000002000000 (OK) (HID1_EL1) [cpu7] Pass: mrs x0, HID3_EL1 = 4180000cf8001fe0 (HID3_EL1) [cpu7] Pass: msr HID3_EL1, x0 = 4180000cf8001fe0 (OK) (HID3_EL1) [cpu7] Pass: mrs x0, HID5_EL1 = 2082df205700ff12 (HID5_EL1) [cpu7] Pass: msr HID5_EL1, x0 = 2082df205700ff12 (OK) (HID5_EL1) [cpu7] Pass: mrs x0, HID9_EL1 = 8100086c000000 (HID9_EL1) [cpu7] Pass: msr HID9_EL1, x0 = 8100086c000000 (OK) (HID9_EL1) [cpu7] Pass: mrs x0, HID11_EL1 = 804000010008000 (HID11_EL1) [cpu7] Pass: msr HID11_EL1, x0 = 804000010008000 (OK) (HID11_EL1) [cpu7] Pass: mrs x0, HID13_EL1 = c332200211010205 (HID13_EL1) [cpu7] Pass: msr HID13_EL1, x0 = c332200211010205 (OK) (HID13_EL1) [cpu7] Pass: mrs x0, HID16_EL1 = 6900000440000000 (HID16_EL1) [cpu7] Pass: msr HID16_EL1, x0 = 6900000440000000 (OK) (HID16_EL1) [cpu7] Pass: mrs x0, HID0_EL1 = 10002990120e0e00 (HID0_EL1) [cpu7] Pass: msr HID0_EL1, x0 = 10002990120e0e00 (OK) (HID0_EL1) [cpu7] Pass: mrs x0, HID7_EL1 = 3110000 (HID7_EL1) [cpu7] Pass: msr HID7_EL1, x0 = 3110000 (OK) (HID7_EL1) [cpu7] Pass: mrs x0, HID7_EL1 = 3110000 (HID7_EL1) [cpu7] Pass: msr HID7_EL1, x0 = 3110000 (OK) (HID7_EL1) [cpu7] Pass: mrs x0, HID9_EL1 = 8100086c000000 (HID9_EL1) [cpu7] Pass: msr HID9_EL1, x0 = 8100086c000000 (OK) (HID9_EL1) [cpu7] Pass: mrs x0, HID18_EL1 = 2000040004000 (HID18_EL1) [cpu7] Pass: msr HID18_EL1, x0 = 2000040004000 (OK) (HID18_EL1) [cpu7] Pass: mrs x0, HID21_EL1 = 1040000 (HID21_EL1) [cpu7] Pass: msr HID21_EL1, x0 = 1040000 (OK) (HID21_EL1) [cpu7] Pass: mrs x0, HID1_EL1 = 1400000002000000 (HID1_EL1) [cpu7] Pass: msr HID1_EL1, x0 = 1400000002000000 (OK) (HID1_EL1) [cpu7] Pass: mrs x0, HID9_EL1 = 8100086c000000 (HID9_EL1) [cpu7] Pass: msr HID9_EL1, x0 = 8100086c000000 (OK) (HID9_EL1) [cpu7] Pass: mrs x0, HID11_EL1 = 804000010008000 (HID11_EL1) [cpu7] Pass: msr HID11_EL1, x0 = 804000010008000 (OK) (HID11_EL1) [cpu7] Pass: mrs x0, HID1_EL1 = 1400000002000000 (HID1_EL1) [cpu7] Pass: msr HID1_EL1, x0 = 1400000002000000 (OK) (HID1_EL1) [cpu7] Pass: mrs x0, HID18_EL1 = 2000040004000 (HID18_EL1) [cpu7] Pass: msr HID18_EL1, x0 = 2000040004000 (OK) (HID18_EL1) [cpu7] Pass: mrs x1, ACC_CFG_EL1 = d (ACC_CFG_EL1) [cpu7] Skip: msr ACC_CFG_EL1, x1 = d [cpu0] CPUSTART W 28e0d4000+4:32 = 0x400 [cpu0] CPUSTART W 28e0d4000+10:32 = 0x4 [cpu0] Starting guest secondary 0:2:2 [cpu0] CPU #8: RVBAR = 0x1001786c000 TTY> HV: Initializing secondary 8 TTY> HV: Entering guest secondary 8 at 0x1001786c000 [cpu0] PT[23d29c044:23d29c048] -> RESERVED PMGR HACK [cpu0] PT[23d29c048:23d29c04c] -> RESERVED CPU STATE HACK [cpu8] Pass: msr OSLAR_EL1, x0 = 0 (OK) (OSLAR_EL1) [cpu8] Pass: mrs x0, HID13_EL1 = c332200211010205 (HID13_EL1) [cpu8] Pass: msr HID13_EL1, x0 = c332200211010205 (OK) (HID13_EL1) [cpu8] Pass: mrs x0, HID14_EL1 = 500000bb8 (HID14_EL1) [cpu8] Pass: msr HID14_EL1, x0 = 500000bb8 (OK) (HID14_EL1) [cpu8] Pass: mrs x0, HID0_EL1 = 10002990120e0e00 (HID0_EL1) [cpu8] Pass: msr HID0_EL1, x0 = 10002990120e0e00 (OK) (HID0_EL1) [cpu8] Pass: mrs x0, HID1_EL1 = 1400000002000000 (HID1_EL1) [cpu8] Pass: msr HID1_EL1, x0 = 1400000002000000 (OK) (HID1_EL1) [cpu8] Pass: mrs x0, HID3_EL1 = 4180000cf8001fe0 (HID3_EL1) [cpu8] Pass: msr HID3_EL1, x0 = 4180000cf8001fe0 (OK) (HID3_EL1) [cpu8] Pass: mrs x0, HID5_EL1 = 2082df205700ff12 (HID5_EL1) [cpu8] Pass: msr HID5_EL1, x0 = 2082df205700ff12 (OK) (HID5_EL1) [cpu8] Pass: mrs x0, HID9_EL1 = 8100086c000000 (HID9_EL1) [cpu8] Pass: msr HID9_EL1, x0 = 8100086c000000 (OK) (HID9_EL1) [cpu8] Pass: mrs x0, HID11_EL1 = 804000010008000 (HID11_EL1) [cpu8] Pass: msr HID11_EL1, x0 = 804000010008000 (OK) (HID11_EL1) [cpu8] Pass: mrs x0, HID13_EL1 = c332200211010205 (HID13_EL1) [cpu8] Pass: msr HID13_EL1, x0 = c332200211010205 (OK) (HID13_EL1) [cpu8] Pass: mrs x0, HID16_EL1 = 6900000440000000 (HID16_EL1) [cpu8] Pass: msr HID16_EL1, x0 = 6900000440000000 (OK) (HID16_EL1) [cpu8] Pass: mrs x0, HID0_EL1 = 10002990120e0e00 (HID0_EL1) [cpu8] Pass: msr HID0_EL1, x0 = 10002990120e0e00 (OK) (HID0_EL1) [cpu8] Pass: mrs x0, HID7_EL1 = 3110000 (HID7_EL1) [cpu8] Pass: msr HID7_EL1, x0 = 3110000 (OK) (HID7_EL1) [cpu8] Pass: mrs x0, HID7_EL1 = 3110000 (HID7_EL1) [cpu8] Pass: msr HID7_EL1, x0 = 3110000 (OK) (HID7_EL1) [cpu8] Pass: mrs x0, HID9_EL1 = 8100086c000000 (HID9_EL1) [cpu8] Pass: msr HID9_EL1, x0 = 8100086c000000 (OK) (HID9_EL1) [cpu8] Pass: mrs x0, HID18_EL1 = 2000040004000 (HID18_EL1) [cpu8] Pass: msr HID18_EL1, x0 = 2000040004000 (OK) (HID18_EL1) [cpu8] Pass: mrs x0, HID21_EL1 = 1040000 (HID21_EL1) [cpu8] Pass: msr HID21_EL1, x0 = 1040000 (OK) (HID21_EL1) [cpu8] Pass: mrs x0, HID1_EL1 = 1400000002000000 (HID1_EL1) [cpu8] Pass: msr HID1_EL1, x0 = 1400000002000000 (OK) (HID1_EL1) [cpu8] Pass: mrs x0, HID9_EL1 = 8100086c000000 (HID9_EL1) [cpu8] Pass: msr HID9_EL1, x0 = 8100086c000000 (OK) (HID9_EL1) [cpu8] Pass: mrs x0, HID11_EL1 = 804000010008000 (HID11_EL1) [cpu8] Pass: msr HID11_EL1, x0 = 804000010008000 (OK) (HID11_EL1) [cpu8] Pass: mrs x0, HID1_EL1 = 1400000002000000 (HID1_EL1) [cpu8] Pass: msr HID1_EL1, x0 = 1400000002000000 (OK) (HID1_EL1) [cpu8] Pass: mrs x0, HID18_EL1 = 2000040004000 (HID18_EL1) [cpu8] Pass: msr HID18_EL1, x0 = 2000040004000 (OK) (HID18_EL1) [cpu8] Pass: mrs x1, ACC_CFG_EL1 = d (ACC_CFG_EL1) [cpu8] Skip: msr ACC_CFG_EL1, x1 = d [cpu0] CPUSTART W 28e0d4000+4:32 = 0x800 [cpu0] CPUSTART W 28e0d4000+10:32 = 0x8 [cpu0] Starting guest secondary 0:2:3 [cpu0] CPU #9: RVBAR = 0x1001786c000 TTY> HV: Initializing secondary 9 TTY> HV: Entering guest secondary 9 at 0x1001786c000 [cpu0] PT[23d29c044:23d29c048] -> RESERVED PMGR HACK [cpu0] PT[23d29c048:23d29c04c] -> RESERVED CPU STATE HACK [cpu9] Pass: msr OSLAR_EL1, x0 = 0 (OK) (OSLAR_EL1) [cpu9] Pass: mrs x0, HID13_EL1 = c332200211010205 (HID13_EL1) [cpu9] Pass: msr HID13_EL1, x0 = c332200211010205 (OK) (HID13_EL1) [cpu9] Pass: mrs x0, HID14_EL1 = 500000bb8 (HID14_EL1) [cpu9] Pass: msr HID14_EL1, x0 = 500000bb8 (OK) (HID14_EL1) [cpu9] Pass: mrs x0, HID0_EL1 = 10002990120e0e00 (HID0_EL1) [cpu9] Pass: msr HID0_EL1, x0 = 10002990120e0e00 (OK) (HID0_EL1) [cpu9] Pass: mrs x0, HID1_EL1 = 1400000002000000 (HID1_EL1) [cpu9] Pass: msr HID1_EL1, x0 = 1400000002000000 (OK) (HID1_EL1) [cpu9] Pass: mrs x0, HID3_EL1 = 4180000cf8001fe0 (HID3_EL1) [cpu9] Pass: msr HID3_EL1, x0 = 4180000cf8001fe0 (OK) (HID3_EL1) [cpu9] Pass: mrs x0, HID5_EL1 = 2082df205700ff12 (HID5_EL1) [cpu9] Pass: msr HID5_EL1, x0 = 2082df205700ff12 (OK) (HID5_EL1) [cpu9] Pass: mrs x0, HID9_EL1 = 8100086c000000 (HID9_EL1) [cpu9] Pass: msr HID9_EL1, x0 = 8100086c000000 (OK) (HID9_EL1) [cpu9] Pass: mrs x0, HID11_EL1 = 804000010008000 (HID11_EL1) [cpu9] Pass: msr HID11_EL1, x0 = 804000010008000 (OK) (HID11_EL1) [cpu9] Pass: mrs x0, HID13_EL1 = c332200211010205 (HID13_EL1) [cpu9] Pass: msr HID13_EL1, x0 = c332200211010205 (OK) (HID13_EL1) [cpu9] Pass: mrs x0, HID16_EL1 = 6900000440000000 (HID16_EL1) [cpu9] Pass: msr HID16_EL1, x0 = 6900000440000000 (OK) (HID16_EL1) [cpu9] Pass: mrs x0, HID0_EL1 = 10002990120e0e00 (HID0_EL1) [cpu9] Pass: msr HID0_EL1, x0 = 10002990120e0e00 (OK) (HID0_EL1) [cpu9] Pass: mrs x0, HID7_EL1 = 3110000 (HID7_EL1) [cpu9] Pass: msr HID7_EL1, x0 = 3110000 (OK) (HID7_EL1) [cpu9] Pass: mrs x0, HID7_EL1 = 3110000 (HID7_EL1) [cpu9] Pass: msr HID7_EL1, x0 = 3110000 (OK) (HID7_EL1) [cpu9] Pass: mrs x0, HID9_EL1 = 8100086c000000 (HID9_EL1) [cpu9] Pass: msr HID9_EL1, x0 = 8100086c000000 (OK) (HID9_EL1) [cpu9] Pass: mrs x0, HID18_EL1 = 2000040004000 (HID18_EL1) [cpu9] Pass: msr HID18_EL1, x0 = 2000040004000 (OK) (HID18_EL1) [cpu9] Pass: mrs x0, HID21_EL1 = 1040000 (HID21_EL1) [cpu9] Pass: msr HID21_EL1, x0 = 1040000 (OK) (HID21_EL1) [cpu9] Pass: mrs x0, HID1_EL1 = 1400000002000000 (HID1_EL1) [cpu9] Pass: msr HID1_EL1, x0 = 1400000002000000 (OK) (HID1_EL1) [cpu9] Pass: mrs x0, HID9_EL1 = 8100086c000000 (HID9_EL1) [cpu9] Pass: msr HID9_EL1, x0 = 8100086c000000 (OK) (HID9_EL1) [cpu9] Pass: mrs x0, HID11_EL1 = 804000010008000 (HID11_EL1) [cpu9] Pass: msr HID11_EL1, x0 = 804000010008000 (OK) (HID11_EL1) [cpu9] Pass: mrs x0, HID1_EL1 = 1400000002000000 (HID1_EL1) [cpu9] Pass: msr HID1_EL1, x0 = 1400000002000000 (OK) (HID1_EL1) [cpu9] Pass: mrs x0, HID18_EL1 = 2000040004000 (HID18_EL1) [cpu9] Pass: msr HID18_EL1, x0 = 2000040004000 (OK) (HID18_EL1) [cpu9] Pass: mrs x1, ACC_CFG_EL1 = d (ACC_CFG_EL1) [cpu9] Skip: msr ACC_CFG_EL1, x1 = d [cpu0] PMGR R 28e0801d8+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR W 28e0801d8+0:32 = 0xf0000ff: Dangerous write [cpu0] PMGR R 28e0801d8+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e580148+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR W 28e580148+0:32 = 0xf0000ff: Dangerous write [cpu0] PMGR R 28e580148+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e580150+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR W 28e580150+0:32 = 0xf0000ff: Dangerous write [cpu0] PMGR R 28e580150+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e580160+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR W 28e580160+0:32 = 0xf0000ff: Dangerous write [cpu0] PMGR R 28e580160+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e580180+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR W 28e580180+0:32 = 0xf0000ff: Dangerous write [cpu0] PMGR R 28e580180+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e0801d8+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR W 28e0801d8+0:32 = 0xf0000ff: Dangerous write [cpu0] PMGR R 28e0801d8+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e0801f0+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR W 28e0801f0+0:32 = 0xf0000ff: Dangerous write [cpu0] PMGR R 28e0801f0+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e080200+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR W 28e080200+0:32 = 0xf0000ff: Dangerous write [cpu0] PMGR R 28e080200+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e080218+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR W 28e080218+0:32 = 0xf0000ff: Dangerous write [cpu0] PMGR R 28e080218+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e0801d8+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR W 28e0801d8+0:32 = 0xf0000ff: Dangerous write [cpu0] PMGR R 28e0801d8+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e0801f0+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR W 28e0801f0+0:32 = 0xf0000ff: Dangerous write [cpu0] PMGR R 28e0801f0+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e080200+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR W 28e080200+0:32 = 0xf0000ff: Dangerous write [cpu0] PMGR R 28e080200+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e080218+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR W 28e080218+0:32 = 0xf0000ff: Dangerous write [cpu0] PMGR R 28e080218+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e0801d8+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR W 28e0801d8+0:32 = 0xf0000ff: Dangerous write [cpu0] PMGR R 28e0801d8+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e0801f0+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR W 28e0801f0+0:32 = 0xf0000ff: Dangerous write [cpu0] PMGR R 28e0801f0+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e080200+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR W 28e080200+0:32 = 0xf0000ff: Dangerous write [cpu0] PMGR R 28e080200+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e080218+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR W 28e080218+0:32 = 0xf0000ff: Dangerous write [cpu0] PMGR R 28e080218+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e0801d8+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR W 28e0801d8+0:32 = 0xf0000ff: Dangerous write [cpu0] PMGR R 28e0801d8+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e0801f0+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR W 28e0801f0+0:32 = 0xf0000ff: Dangerous write [cpu0] PMGR R 28e0801f0+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e080200+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR W 28e080200+0:32 = 0xf0000ff: Dangerous write [cpu0] PMGR R 28e080200+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e080218+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR W 28e080218+0:32 = 0xf0000ff: Dangerous write [cpu0] PMGR R 28e080218+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e0801d8+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR W 28e0801d8+0:32 = 0xf0000ff: Dangerous write [cpu0] PMGR R 28e0801d8+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e0801f0+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR W 28e0801f0+0:32 = 0xf0000ff: Dangerous write [cpu0] PMGR R 28e0801f0+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e080200+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR W 28e080200+0:32 = 0xf0000ff: Dangerous write [cpu0] PMGR R 28e080200+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e080218+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR W 28e080218+0:32 = 0xf0000ff: Dangerous write [cpu0] PMGR R 28e080218+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e0801d8+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR W 28e0801d8+0:32 = 0xf0000ff: Dangerous write [cpu0] PMGR R 28e0801d8+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e0801f0+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR W 28e0801f0+0:32 = 0xf0000ff: Dangerous write [cpu0] PMGR R 28e0801f0+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e080200+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR W 28e080200+0:32 = 0xf0000ff: Dangerous write [cpu0] PMGR R 28e080200+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e080218+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR W 28e080218+0:32 = 0xf0000ff: Dangerous write [cpu0] PMGR R 28e080218+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e0801d8+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR W 28e0801d8+0:32 = 0xf0000ff: Dangerous write [cpu0] PMGR R 28e0801d8+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e0801f0+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR W 28e0801f0+0:32 = 0xf0000ff: Dangerous write [cpu0] PMGR R 28e0801f0+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e080200+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR W 28e080200+0:32 = 0xf0000ff: Dangerous write [cpu0] PMGR R 28e080200+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e080218+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR W 28e080218+0:32 = 0xf0000ff: Dangerous write [cpu0] PMGR R 28e080218+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e0801d8+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR W 28e0801d8+0:32 = 0xf0000ff: Dangerous write [cpu0] PMGR R 28e0801d8+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e0801f0+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR W 28e0801f0+0:32 = 0xf0000ff: Dangerous write [cpu0] PMGR R 28e0801f0+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e080200+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR W 28e080200+0:32 = 0xf0000ff: Dangerous write [cpu0] PMGR R 28e080200+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e080218+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR W 28e080218+0:32 = 0xf0000ff: Dangerous write [cpu0] PMGR R 28e080218+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e0801d8+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR W 28e0801d8+0:32 = 0xf0000ff: Dangerous write [cpu0] PMGR R 28e0801d8+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e0801f0+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR W 28e0801f0+0:32 = 0xf0000ff: Dangerous write [cpu0] PMGR R 28e0801f0+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e080200+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR W 28e080200+0:32 = 0xf0000ff: Dangerous write [cpu0] PMGR R 28e080200+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e0801d8+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR W 28e0801d8+0:32 = 0xf0000ff: Dangerous write [cpu0] PMGR R 28e0801d8+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e580148+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR W 28e580148+0:32 = 0xf0000ff: Dangerous write [cpu0] PMGR R 28e580148+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e580150+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR W 28e580150+0:32 = 0xf0000ff: Dangerous write [cpu0] PMGR R 28e580150+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e580160+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR W 28e580160+0:32 = 0xf0000ff: Dangerous write [cpu0] PMGR R 28e580160+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] [0x00000100178763fc] MMIO: W.4 0x3860ec004 (isp0[0], offset 0x20ec004) = 0x1 [cpu0] [0x0000010017876440] MMIO: W.8 0x3860ec008 (isp0[0], offset 0x20ec008) = 0x10000a58000 [cpu0] [0x0000010017876484] MMIO: W.8 0x3860ec010 (isp0[0], offset 0x20ec010) = 0x100013d7fff [cpu0] [0x0000010017876494] MMIO: W.4 0x3860ec000 (isp0[0], offset 0x20ec000) = 0x11 [cpu0] [0x00000100178763fc] MMIO: W.4 0x3860ec044 (isp0[0], offset 0x20ec044) = 0x1 [cpu0] [0x0000010017876440] MMIO: W.8 0x3860ec048 (isp0[0], offset 0x20ec048) = 0x1f000000000 [cpu0] [0x0000010017876484] MMIO: W.8 0x3860ec050 (isp0[0], offset 0x20ec050) = 0x1f0ffffffff [cpu0] [0x0000010017876494] MMIO: W.4 0x3860ec040 (isp0[0], offset 0x20ec040) = 0x33 [cpu0] [0x00000100178763fc] MMIO: W.4 0x3860ec084 (isp0[0], offset 0x20ec084) = 0x1 [cpu0] [0x0000010017876440] MMIO: W.8 0x3860ec088 (isp0[0], offset 0x20ec088) = 0x28e584000 [cpu0] [0x0000010017876484] MMIO: W.8 0x3860ec090 (isp0[0], offset 0x20ec090) = 0x28e584043 [cpu0] [0x0000010017876494] MMIO: W.4 0x3860ec080 (isp0[0], offset 0x20ec080) = 0x31 [cpu0] [0x00000100178763fc] MMIO: W.4 0x3860ec0c4 (isp0[0], offset 0x20ec0c4) = 0x1 [cpu0] [0x0000010017876440] MMIO: W.8 0x3860ec0c8 (isp0[0], offset 0x20ec0c8) = 0x28e0b8000 [cpu0] [0x0000010017876484] MMIO: W.8 0x3860ec0d0 (isp0[0], offset 0x20ec0d0) = 0x28e0bffff [cpu0] [0x0000010017876494] MMIO: W.4 0x3860ec0c0 (isp0[0], offset 0x20ec0c0) = 0x31 [cpu0] [0x00000100178763fc] MMIO: W.4 0x3860ec104 (isp0[0], offset 0x20ec104) = 0x1 [cpu0] [0x0000010017876440] MMIO: W.8 0x3860ec108 (isp0[0], offset 0x20ec108) = 0x39a000000 [cpu0] [0x0000010017876484] MMIO: W.8 0x3860ec110 (isp0[0], offset 0x20ec110) = 0x39a00004b [cpu0] [0x0000010017876494] MMIO: W.4 0x3860ec100 (isp0[0], offset 0x20ec100) = 0x31 [cpu0] [0x00000100178763fc] MMIO: W.4 0x3860ec144 (isp0[0], offset 0x20ec144) = 0x1 [cpu0] [0x0000010017876440] MMIO: W.8 0x3860ec148 (isp0[0], offset 0x20ec148) = 0x39b010000 [cpu0] [0x0000010017876484] MMIO: W.8 0x3860ec150 (isp0[0], offset 0x20ec150) = 0x39b0130b3 [cpu0] [0x0000010017876494] MMIO: W.4 0x3860ec140 (isp0[0], offset 0x20ec140) = 0x31 [cpu0] [0x00000100178763fc] MMIO: W.4 0x3860ec184 (isp0[0], offset 0x20ec184) = 0x1 [cpu0] [0x0000010017876440] MMIO: W.8 0x3860ec188 (isp0[0], offset 0x20ec188) = 0x39b014000 [cpu0] [0x0000010017876484] MMIO: W.8 0x3860ec190 (isp0[0], offset 0x20ec190) = 0x39b0170b3 [cpu0] [0x0000010017876494] MMIO: W.4 0x3860ec180 (isp0[0], offset 0x20ec180) = 0x31 [cpu0] [0x00000100178763fc] MMIO: W.4 0x3860ec1c4 (isp0[0], offset 0x20ec1c4) = 0x1 [cpu0] [0x0000010017876440] MMIO: W.8 0x3860ec1c8 (isp0[0], offset 0x20ec1c8) = 0x39b018000 [cpu0] [0x0000010017876484] MMIO: W.8 0x3860ec1d0 (isp0[0], offset 0x20ec1d0) = 0x39b01b0b3 [cpu0] [0x0000010017876494] MMIO: W.4 0x3860ec1c0 (isp0[0], offset 0x20ec1c0) = 0x31 [cpu0] [0x00000100178763fc] MMIO: W.4 0x3860ec204 (isp0[0], offset 0x20ec204) = 0x1 [cpu0] [0x0000010017876440] MMIO: W.8 0x3860ec208 (isp0[0], offset 0x20ec208) = 0x28ec3c000 [cpu0] [0x0000010017876484] MMIO: W.8 0x3860ec210 (isp0[0], offset 0x20ec210) = 0x28ec3c003 [cpu0] [0x0000010017876494] MMIO: W.4 0x3860ec200 (isp0[0], offset 0x20ec200) = 0x31 [cpu0] [0x00000100178763fc] MMIO: W.4 0x3860ec244 (isp0[0], offset 0x20ec244) = 0x1 [cpu0] [0x0000010017876440] MMIO: W.8 0x3860ec248 (isp0[0], offset 0x20ec248) = 0x29342c000 [cpu0] [0x0000010017876484] MMIO: W.8 0x3860ec250 (isp0[0], offset 0x20ec250) = 0x293448003 [cpu0] [0x0000010017876494] MMIO: W.4 0x3860ec240 (isp0[0], offset 0x20ec240) = 0x31 [cpu0] [0x00000100178763fc] MMIO: W.4 0x3860ec284 (isp0[0], offset 0x20ec284) = 0x1 [cpu0] [0x0000010017876440] MMIO: W.8 0x3860ec288 (isp0[0], offset 0x20ec288) = 0x285460000 [cpu0] [0x0000010017876484] MMIO: W.8 0x3860ec290 (isp0[0], offset 0x20ec290) = 0x285460003 [cpu0] [0x0000010017876494] MMIO: W.4 0x3860ec280 (isp0[0], offset 0x20ec280) = 0x31 [cpu0] [0x00000100178763fc] MMIO: W.4 0x3860ec2c4 (isp0[0], offset 0x20ec2c4) = 0x1 [cpu0] [0x0000010017876440] MMIO: W.8 0x3860ec2c8 (isp0[0], offset 0x20ec2c8) = 0x200004000 [cpu0] [0x0000010017876484] MMIO: W.8 0x3860ec2d0 (isp0[0], offset 0x20ec2d0) = 0x2000d63f8 [cpu0] [0x0000010017876494] MMIO: W.4 0x3860ec2c0 (isp0[0], offset 0x20ec2c0) = 0x31 [cpu0] [0x00000100178763fc] MMIO: W.4 0x3860ec304 (isp0[0], offset 0x20ec304) = 0x1 [cpu0] [0x0000010017876440] MMIO: W.8 0x3860ec308 (isp0[0], offset 0x20ec308) = 0x201004000 [cpu0] [0x0000010017876484] MMIO: W.8 0x3860ec310 (isp0[0], offset 0x20ec310) = 0x2010d63f8 [cpu0] [0x0000010017876494] MMIO: W.4 0x3860ec300 (isp0[0], offset 0x20ec300) = 0x31 [cpu0] [0x00000100178763fc] MMIO: W.4 0x3860ec344 (isp0[0], offset 0x20ec344) = 0x1 [cpu0] [0x0000010017876440] MMIO: W.8 0x3860ec348 (isp0[0], offset 0x20ec348) = 0x202004000 [cpu0] [0x0000010017876484] MMIO: W.8 0x3860ec350 (isp0[0], offset 0x20ec350) = 0x2020d63f8 [cpu0] [0x0000010017876494] MMIO: W.4 0x3860ec340 (isp0[0], offset 0x20ec340) = 0x31 [cpu0] [0x00000100178763fc] MMIO: W.4 0x3860ec384 (isp0[0], offset 0x20ec384) = 0x1 [cpu0] [0x0000010017876440] MMIO: W.8 0x3860ec388 (isp0[0], offset 0x20ec388) = 0x203004000 [cpu0] [0x0000010017876484] MMIO: W.8 0x3860ec390 (isp0[0], offset 0x20ec390) = 0x2030d63f8 [cpu0] [0x0000010017876494] MMIO: W.4 0x3860ec380 (isp0[0], offset 0x20ec380) = 0x31 [cpu0] [0x00000100178763fc] MMIO: W.4 0x3860ec3c4 (isp0[0], offset 0x20ec3c4) = 0x1 [cpu0] [0x0000010017876440] MMIO: W.8 0x3860ec3c8 (isp0[0], offset 0x20ec3c8) = 0x28e3d0000 [cpu0] [0x0000010017876484] MMIO: W.8 0x3860ec3d0 (isp0[0], offset 0x20ec3d0) = 0x28e3d0bfc [cpu0] [0x0000010017876494] MMIO: W.4 0x3860ec3c0 (isp0[0], offset 0x20ec3c0) = 0x31 [cpu0] PMGR R 28e0801d8+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR W 28e0801d8+0:32 = 0xf0000ff: Dangerous write [cpu0] PMGR R 28e0801d8+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e580148+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR W 28e580148+0:32 = 0xf0000ff: Dangerous write [cpu0] PMGR R 28e580148+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e580150+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR W 28e580150+0:32 = 0xf0000ff: Dangerous write [cpu0] PMGR R 28e580150+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e580160+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR W 28e580160+0:32 = 0xf0000ff: Dangerous write [cpu0] PMGR R 28e580160+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] [0x0000010017882020] MMIO: W.4 0x3860e80fc (isp0[0], offset 0x20e80fc) = 0x1 [cpu0] [0x0000010017882030] MMIO: W.4 0x3860e82f0 (isp0[0], offset 0x20e82f0) = 0x0 [cpu0] [0x0000010017882040] MMIO: W.4 0x3860e8034 (isp0[0], offset 0x20e8034) = 0xffffffff [cpu0] [0x0000010017882050] MMIO: W.4 0x3860e8020 (isp0[0], offset 0x20e8020) = 0x100000 [cpu0] [0x0000010017882088] MMIO: R.4 0x3860e8060 (isp0[0], offset 0x20e8060) = 0xec016100 [cpu0] [0x000001001788208c] MMIO: R.4 0x3860e8060 (isp0[0], offset 0x20e8060) = 0xec016100 [cpu0] [0x0000010017882098] MMIO: W.4 0x3860e8060 (isp0[0], offset 0x20e8060) = 0xec006100 [cpu0] [0x0000010017882088] MMIO: R.4 0x3860e8068 (isp0[0], offset 0x20e8068) = 0xf0f0f [cpu0] [0x000001001788208c] MMIO: R.4 0x3860e8068 (isp0[0], offset 0x20e8068) = 0xf0f0f [cpu0] [0x0000010017882098] MMIO: W.4 0x3860e8068 (isp0[0], offset 0x20e8068) = 0xf0f0f [cpu0] [0x0000010017882088] MMIO: R.4 0x3860e806c (isp0[0], offset 0x20e806c) = 0x80808 [cpu0] [0x000001001788208c] MMIO: R.4 0x3860e806c (isp0[0], offset 0x20e806c) = 0x80808 [cpu0] [0x0000010017882098] MMIO: W.4 0x3860e806c (isp0[0], offset 0x20e806c) = 0x80808 [cpu0] [0x00000100178820b0] MMIO: W.4 0x3860e8100 (isp0[0], offset 0x20e8100) = 0x80 [cpu0] [0x00000100178820c0] MMIO: W.4 0x3860e813c (isp0[0], offset 0x20e813c) = 0x20000 [cpu0] [0x0000010017882020] MMIO: W.4 0x3860f40fc (isp0[0], offset 0x20f40fc) = 0x1 [cpu0] [0x0000010017882030] MMIO: W.4 0x3860f42f0 (isp0[0], offset 0x20f42f0) = 0x0 [cpu0] [0x0000010017882040] MMIO: W.4 0x3860f4034 (isp0[0], offset 0x20f4034) = 0xffffffff [cpu0] [0x0000010017882050] MMIO: W.4 0x3860f4020 (isp0[0], offset 0x20f4020) = 0x100000 [cpu0] [0x0000010017882088] MMIO: R.4 0x3860f4060 (isp0[0], offset 0x20f4060) = 0x1e010000 [cpu0] [0x000001001788208c] MMIO: R.4 0x3860f4060 (isp0[0], offset 0x20f4060) = 0x1e010000 [cpu0] [0x0000010017882098] MMIO: W.4 0x3860f4060 (isp0[0], offset 0x20f4060) = 0xec006100 [cpu0] [0x0000010017882088] MMIO: R.4 0x3860f4068 (isp0[0], offset 0x20f4068) = 0x20202 [cpu0] [0x000001001788208c] MMIO: R.4 0x3860f4068 (isp0[0], offset 0x20f4068) = 0x20202 [cpu0] [0x0000010017882098] MMIO: W.4 0x3860f4068 (isp0[0], offset 0x20f4068) = 0xf0f0f [cpu0] [0x0000010017882088] MMIO: R.4 0x3860f406c (isp0[0], offset 0x20f406c) = 0x0 [cpu0] [0x000001001788208c] MMIO: R.4 0x3860f406c (isp0[0], offset 0x20f406c) = 0x0 [cpu0] [0x0000010017882098] MMIO: W.4 0x3860f406c (isp0[0], offset 0x20f406c) = 0x80808 [cpu0] [0x00000100178820b0] MMIO: W.4 0x3860f4100 (isp0[0], offset 0x20f4100) = 0x80 [cpu0] [0x00000100178820c0] MMIO: W.4 0x3860f413c (isp0[0], offset 0x20f413c) = 0x20000 [cpu0] [0x0000010017882020] MMIO: W.4 0x3860fc0fc (isp0[0], offset 0x20fc0fc) = 0x1 [cpu0] [0x0000010017882030] MMIO: W.4 0x3860fc2f0 (isp0[0], offset 0x20fc2f0) = 0x0 [cpu0] [0x0000010017882040] MMIO: W.4 0x3860fc034 (isp0[0], offset 0x20fc034) = 0xffffffff [cpu0] [0x0000010017882050] MMIO: W.4 0x3860fc020 (isp0[0], offset 0x20fc020) = 0x100000 [cpu0] [0x0000010017882088] MMIO: R.4 0x3860fc060 (isp0[0], offset 0x20fc060) = 0x1e010000 [cpu0] [0x000001001788208c] MMIO: R.4 0x3860fc060 (isp0[0], offset 0x20fc060) = 0x1e010000 [cpu0] [0x0000010017882098] MMIO: W.4 0x3860fc060 (isp0[0], offset 0x20fc060) = 0x9e006100 [cpu0] [0x0000010017882088] MMIO: R.4 0x3860fc068 (isp0[0], offset 0x20fc068) = 0x20202 [cpu0] [0x000001001788208c] MMIO: R.4 0x3860fc068 (isp0[0], offset 0x20fc068) = 0x20202 [cpu0] [0x0000010017882098] MMIO: W.4 0x3860fc068 (isp0[0], offset 0x20fc068) = 0xf0f0f [cpu0] [0x0000010017882088] MMIO: R.4 0x3860fc06c (isp0[0], offset 0x20fc06c) = 0x0 [cpu0] [0x000001001788208c] MMIO: R.4 0x3860fc06c (isp0[0], offset 0x20fc06c) = 0x0 [cpu0] [0x0000010017882098] MMIO: W.4 0x3860fc06c (isp0[0], offset 0x20fc06c) = 0x80808 [cpu0] [0x00000100178820b0] MMIO: W.4 0x3860fc100 (isp0[0], offset 0x20fc100) = 0x80 [cpu0] [0x00000100178820c0] MMIO: W.4 0x3860fc13c (isp0[0], offset 0x20fc13c) = 0x20000 [cpu0] PMGR R 28e0801d8+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR W 28e0801d8+0:32 = 0xf0000ff: Dangerous write [cpu0] PMGR R 28e0801d8+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e580148+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR W 28e580148+0:32 = 0xf0000ff: Dangerous write [cpu0] PMGR R 28e580148+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e580150+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR W 28e580150+0:32 = 0xf0000ff: Dangerous write [cpu0] PMGR R 28e580150+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e580160+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR W 28e580160+0:32 = 0xf0000ff: Dangerous write [cpu0] PMGR R 28e580160+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e580180+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR W 28e580180+0:32 = 0xf0000ff: Dangerous write [cpu0] PMGR R 28e580180+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e580230+0:32 = 0xff -> 0xff [cpu0] PMGR W 28e580230+0:32 = 0xff: Dangerous write [cpu0] PMGR R 28e580230+0:32 = 0xff -> 0xff [cpu0] PMGR R 28e580240+0:32 = 0xff -> 0xff [cpu0] PMGR W 28e580240+0:32 = 0xff: Dangerous write [cpu0] PMGR R 28e580240+0:32 = 0xff -> 0xff [cpu0] PMGR R 28e0801d8+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR W 28e0801d8+0:32 = 0xf0000ff: Dangerous write [cpu0] PMGR R 28e0801d8+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e580148+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR W 28e580148+0:32 = 0xf0000ff: Dangerous write [cpu0] PMGR R 28e580148+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e580150+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR W 28e580150+0:32 = 0xf0000ff: Dangerous write [cpu0] PMGR R 28e580150+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e580160+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR W 28e580160+0:32 = 0xf0000ff: Dangerous write [cpu0] PMGR R 28e580160+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e580180+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR W 28e580180+0:32 = 0xf0000ff: Dangerous write [cpu0] PMGR R 28e580180+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e580230+0:32 = 0xff -> 0xff [cpu0] PMGR W 28e580230+0:32 = 0xff: Dangerous write [cpu0] PMGR R 28e580230+0:32 = 0xff -> 0xff [cpu0] PMGR R 28e580240+0:32 = 0xff -> 0xff [cpu0] PMGR W 28e580240+0:32 = 0xff: Dangerous write [cpu0] PMGR R 28e580240+0:32 = 0xff -> 0xff [cpu0] PMGR R 28e580150+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR W 28e580150+0:32 = 0xf0000ff: Dangerous write [cpu0] PMGR R 28e580150+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e0801d8+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR W 28e0801d8+0:32 = 0xf0000ff: Dangerous write [cpu0] PMGR R 28e0801d8+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e0801f0+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR W 28e0801f0+0:32 = 0xf0000ff: Dangerous write [cpu0] PMGR R 28e0801f0+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e080200+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR W 28e080200+0:32 = 0xf0000ff: Dangerous write [cpu0] PMGR R 28e080200+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e580180+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR W 28e580180+0:32 = 0xf0000ff: Dangerous write [cpu0] PMGR R 28e580180+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e580180+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR W 28e580180+0:32 = 0xf0000ff: Dangerous write [cpu0] PMGR R 28e580180+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e080200+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR W 28e080200+0:32 = 0xf0000ff: Dangerous write [cpu0] PMGR R 28e080200+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e080218+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR W 28e080218+0:32 = 0xf0000ff: Dangerous write [cpu0] PMGR R 28e080218+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e080218+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR W 28e080218+0:32 = 0xf0000ff: Dangerous write [cpu0] PMGR R 28e080218+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e0801d8+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR W 28e0801d8+0:32 = 0xf0000ff: Dangerous write [cpu0] PMGR R 28e0801d8+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e0801f0+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR W 28e0801f0+0:32 = 0xf0000ff: Dangerous write [cpu0] PMGR R 28e0801f0+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e080200+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR W 28e080200+0:32 = 0xf0000ff: Dangerous write [cpu0] PMGR R 28e080200+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e080218+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR W 28e080218+0:32 = 0xf0000ff: Dangerous write [cpu0] PMGR R 28e080218+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e0801d8+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR W 28e0801d8+0:32 = 0xf0000ff: Dangerous write [cpu0] PMGR R 28e0801d8+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e0801f0+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR W 28e0801f0+0:32 = 0xf0000ff: Dangerous write [cpu0] PMGR R 28e0801f0+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e080200+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR W 28e080200+0:32 = 0xf0000ff: Dangerous write [cpu0] PMGR R 28e080200+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e0801d8+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR W 28e0801d8+0:32 = 0xf0000ff: Dangerous write [cpu0] PMGR R 28e0801d8+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e0801f0+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR W 28e0801f0+0:32 = 0xf0000ff: Dangerous write [cpu0] PMGR R 28e0801f0+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e080200+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR W 28e080200+0:32 = 0xf0000ff: Dangerous write [cpu0] PMGR R 28e080200+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e080218+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR W 28e080218+0:32 = 0xf0000ff: Dangerous write [cpu0] PMGR R 28e080218+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e0801d8+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR W 28e0801d8+0:32 = 0xf0000ff: Dangerous write [cpu0] PMGR R 28e0801d8+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e0801f0+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR W 28e0801f0+0:32 = 0xf0000ff: Dangerous write [cpu0] PMGR R 28e0801f0+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e080200+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR W 28e080200+0:32 = 0xf0000ff: Dangerous write [cpu0] PMGR R 28e080200+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e080218+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR W 28e080218+0:32 = 0xf0000ff: Dangerous write [cpu0] PMGR R 28e080218+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e0801d8+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR W 28e0801d8+0:32 = 0xf0000ff: Dangerous write [cpu0] PMGR R 28e0801d8+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e0801f0+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR W 28e0801f0+0:32 = 0xf0000ff: Dangerous write [cpu0] PMGR R 28e0801f0+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e080200+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR W 28e080200+0:32 = 0xf0000ff: Dangerous write [cpu0] PMGR R 28e080200+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e080218+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR W 28e080218+0:32 = 0xf0000ff: Dangerous write [cpu0] PMGR R 28e080218+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e0801d8+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR W 28e0801d8+0:32 = 0xf0000ff: Dangerous write [cpu0] PMGR R 28e0801d8+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e0801f0+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR W 28e0801f0+0:32 = 0xf0000ff: Dangerous write [cpu0] PMGR R 28e0801f0+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e080200+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR W 28e080200+0:32 = 0xf0000ff: Dangerous write [cpu0] PMGR R 28e080200+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e080218+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR W 28e080218+0:32 = 0xf0000ff: Dangerous write [cpu0] PMGR R 28e080218+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e0801d8+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR W 28e0801d8+0:32 = 0xf0000ff: Dangerous write [cpu0] PMGR R 28e0801d8+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e0801f0+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR W 28e0801f0+0:32 = 0xf0000ff: Dangerous write [cpu0] PMGR R 28e0801f0+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e080200+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR W 28e080200+0:32 = 0xf0000ff: Dangerous write [cpu0] PMGR R 28e080200+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e080218+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR W 28e080218+0:32 = 0xf0000ff: Dangerous write [cpu0] PMGR R 28e080218+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e0801d8+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR W 28e0801d8+0:32 = 0xf0000ff: Dangerous write [cpu0] PMGR R 28e0801d8+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e580148+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR W 28e580148+0:32 = 0xf0000ff: Dangerous write [cpu0] PMGR R 28e580148+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 28e580150+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR W 28e580150+0:32 = 0xf0000ff: Dangerous write [cpu0] PMGR R 28e580150+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] Shadow: msr MDSCR_EL1, x1 = 1000 [cpu1] Shadow: msr MDSCR_EL1, x1 = 1000 [cpu2] Shadow: msr MDSCR_EL1, x1 = 1000 [cpu3] Shadow: msr MDSCR_EL1, x1 = 1000 [cpu4] Shadow: msr MDSCR_EL1, x1 = 1000 [cpu5] Shadow: msr MDSCR_EL1, x1 = 1000 [cpu6] Shadow: msr MDSCR_EL1, x1 = 1000 [cpu7] Shadow: msr MDSCR_EL1, x1 = 1000 [cpu8] Shadow: msr MDSCR_EL1, x1 = 1000 [cpu9] Shadow: msr MDSCR_EL1, x1 = 1000 [cpu0] Pass: msr OSDLR_EL1, x31 = 0 (OK) (OSDLR_EL1) [cpu0] Pass: msr OSLAR_EL1, x31 = 0 (OK) (OSLAR_EL1) [cpu1] Pass: msr OSDLR_EL1, x31 = 0 (OK) (OSDLR_EL1) [cpu1] Pass: msr OSLAR_EL1, x31 = 0 (OK) (OSLAR_EL1) [cpu2] Pass: msr OSDLR_EL1, x31 = 0 (OK) (OSDLR_EL1) [cpu2] Pass: msr OSLAR_EL1, x31 = 0 (OK) (OSLAR_EL1) [cpu3] Pass: msr OSDLR_EL1, x31 = 0 (OK) (OSDLR_EL1) [cpu3] Pass: msr OSLAR_EL1, x31 = 0 (OK) (OSLAR_EL1) [cpu4] Pass: msr OSDLR_EL1, x31 = 0 (OK) (OSDLR_EL1) [cpu4] Pass: msr OSLAR_EL1, x31 = 0 (OK) (OSLAR_EL1) [cpu5] Pass: msr OSDLR_EL1, x31 = 0 (OK) (OSDLR_EL1) [cpu5] Pass: msr OSLAR_EL1, x31 = 0 (OK) (OSLAR_EL1) [cpu6] Pass: msr OSDLR_EL1, x31 = 0 (OK) (OSDLR_EL1) [cpu6] Pass: msr OSLAR_EL1, x31 = 0 (OK) (OSLAR_EL1) [cpu7] Pass: msr OSDLR_EL1, x31 = 0 (OK) (OSDLR_EL1) [cpu7] Pass: msr OSLAR_EL1, x31 = 0 (OK) (OSLAR_EL1) [cpu8] Pass: msr OSDLR_EL1, x31 = 0 (OK) (OSDLR_EL1) [cpu8] Pass: msr OSLAR_EL1, x31 = 0 (OK) (OSLAR_EL1) [cpu9] Pass: msr OSDLR_EL1, x31 = 0 (OK) (OSDLR_EL1) [cpu9] Pass: msr OSLAR_EL1, x31 = 0 (OK) (OSLAR_EL1) [cpu0] Shadow: msr DBGBCR15_EL1, x2 = 0 [cpu0] Shadow: msr DBGBVR15_EL1, x2 = 0 [cpu0] Shadow: msr s2_0_c0_c1_5, x2 = 0 [cpu0] Shadow: msr s2_0_c0_c1_4, x2 = 0 [cpu0] Shadow: msr s2_0_c0_c2_5, x2 = 0 [cpu0] Shadow: msr s2_0_c0_c2_4, x2 = 0 [cpu0] Shadow: msr s2_0_c0_c3_5, x2 = 0 [cpu0] Shadow: msr s2_0_c0_c3_4, x2 = 0 [cpu0] Shadow: msr s2_0_c0_c4_5, x2 = 0 [cpu0] Shadow: msr s2_0_c0_c4_4, x2 = 0 [cpu0] Pass: msr s2_0_c0_c5_5, x2 = 0 (OK) (s2_0_c0_c5_5) [cpu0] Pass: msr s2_0_c0_c5_4, x2 = 0 (OK) (s2_0_c0_c5_4) [cpu0] Shadow: msr DBGWCR15_EL1, x2 = 0 [cpu0] Shadow: msr DBGWVR15_EL1, x2 = 0 [cpu0] Shadow: msr s2_0_c0_c1_7, x2 = 0 [cpu0] Shadow: msr s2_0_c0_c1_6, x2 = 0 [cpu0] Shadow: msr s2_0_c0_c2_7, x2 = 0 [cpu0] Shadow: msr s2_0_c0_c2_6, x2 = 0 [cpu0] Shadow: msr s2_0_c0_c3_7, x2 = 0 [cpu0] Shadow: msr s2_0_c0_c3_6, x2 = 0 [cpu1] Shadow: msr DBGBCR15_EL1, x2 = 0 [cpu1] Shadow: msr DBGBVR15_EL1, x2 = 0 [cpu1] Shadow: msr s2_0_c0_c1_5, x2 = 0 [cpu1] Shadow: msr s2_0_c0_c1_4, x2 = 0 [cpu1] Shadow: msr s2_0_c0_c2_5, x2 = 0 [cpu1] Shadow: msr s2_0_c0_c2_4, x2 = 0 [cpu1] Shadow: msr s2_0_c0_c3_5, x2 = 0 [cpu1] Shadow: msr s2_0_c0_c3_4, x2 = 0 [cpu1] Shadow: msr s2_0_c0_c4_5, x2 = 0 [cpu1] Shadow: msr s2_0_c0_c4_4, x2 = 0 [cpu1] Pass: msr s2_0_c0_c5_5, x2 = 0 (OK) (s2_0_c0_c5_5) [cpu1] Pass: msr s2_0_c0_c5_4, x2 = 0 (OK) (s2_0_c0_c5_4) [cpu1] Shadow: msr DBGWCR15_EL1, x2 = 0 [cpu1] Shadow: msr DBGWVR15_EL1, x2 = 0 [cpu1] Shadow: msr s2_0_c0_c1_7, x2 = 0 [cpu1] Shadow: msr s2_0_c0_c1_6, x2 = 0 [cpu1] Shadow: msr s2_0_c0_c2_7, x2 = 0 [cpu1] Shadow: msr s2_0_c0_c2_6, x2 = 0 [cpu1] Shadow: msr s2_0_c0_c3_7, x2 = 0 [cpu1] Shadow: msr s2_0_c0_c3_6, x2 = 0 [cpu2] Shadow: msr DBGBCR15_EL1, x2 = 0 [cpu2] Shadow: msr DBGBVR15_EL1, x2 = 0 [cpu2] Shadow: msr s2_0_c0_c1_5, x2 = 0 [cpu2] Shadow: msr s2_0_c0_c1_4, x2 = 0 [cpu2] Shadow: msr s2_0_c0_c2_5, x2 = 0 [cpu2] Shadow: msr s2_0_c0_c2_4, x2 = 0 [cpu2] Shadow: msr s2_0_c0_c3_5, x2 = 0 [cpu2] Shadow: msr s2_0_c0_c3_4, x2 = 0 [cpu2] Shadow: msr s2_0_c0_c4_5, x2 = 0 [cpu2] Shadow: msr s2_0_c0_c4_4, x2 = 0 [cpu2] Pass: msr s2_0_c0_c5_5, x2 = 0 (OK) (s2_0_c0_c5_5) [cpu2] Pass: msr s2_0_c0_c5_4, x2 = 0 (OK) (s2_0_c0_c5_4) [cpu2] Shadow: msr DBGWCR15_EL1, x2 = 0 [cpu2] Shadow: msr DBGWVR15_EL1, x2 = 0 [cpu2] Shadow: msr s2_0_c0_c1_7, x2 = 0 [cpu2] Shadow: msr s2_0_c0_c1_6, x2 = 0 [cpu2] Shadow: msr s2_0_c0_c2_7, x2 = 0 [cpu2] Shadow: msr s2_0_c0_c2_6, x2 = 0 [cpu2] Shadow: msr s2_0_c0_c3_7, x2 = 0 [cpu2] Shadow: msr s2_0_c0_c3_6, x2 = 0 [cpu3] Shadow: msr DBGBCR15_EL1, x2 = 0 [cpu3] Shadow: msr DBGBVR15_EL1, x2 = 0 [cpu3] Shadow: msr s2_0_c0_c1_5, x2 = 0 [cpu3] Shadow: msr s2_0_c0_c1_4, x2 = 0 [cpu3] Shadow: msr s2_0_c0_c2_5, x2 = 0 [cpu3] Shadow: msr s2_0_c0_c2_4, x2 = 0 [cpu3] Shadow: msr s2_0_c0_c3_5, x2 = 0 [cpu3] Shadow: msr s2_0_c0_c3_4, x2 = 0 [cpu3] Shadow: msr s2_0_c0_c4_5, x2 = 0 [cpu3] Shadow: msr s2_0_c0_c4_4, x2 = 0 [cpu3] Pass: msr s2_0_c0_c5_5, x2 = 0 (OK) (s2_0_c0_c5_5) [cpu3] Pass: msr s2_0_c0_c5_4, x2 = 0 (OK) (s2_0_c0_c5_4) [cpu3] Shadow: msr DBGWCR15_EL1, x2 = 0 [cpu3] Shadow: msr DBGWVR15_EL1, x2 = 0 [cpu3] Shadow: msr s2_0_c0_c1_7, x2 = 0 [cpu3] Shadow: msr s2_0_c0_c1_6, x2 = 0 [cpu3] Shadow: msr s2_0_c0_c2_7, x2 = 0 [cpu3] Shadow: msr s2_0_c0_c2_6, x2 = 0 [cpu3] Shadow: msr s2_0_c0_c3_7, x2 = 0 [cpu3] Shadow: msr s2_0_c0_c3_6, x2 = 0 [cpu4] Shadow: msr DBGBCR15_EL1, x2 = 0 [cpu4] Shadow: msr DBGBVR15_EL1, x2 = 0 [cpu4] Shadow: msr s2_0_c0_c1_5, x2 = 0 [cpu4] Shadow: msr s2_0_c0_c1_4, x2 = 0 [cpu4] Shadow: msr s2_0_c0_c2_5, x2 = 0 [cpu4] Shadow: msr s2_0_c0_c2_4, x2 = 0 [cpu4] Shadow: msr s2_0_c0_c3_5, x2 = 0 [cpu4] Shadow: msr s2_0_c0_c3_4, x2 = 0 [cpu4] Shadow: msr s2_0_c0_c4_5, x2 = 0 [cpu4] Shadow: msr s2_0_c0_c4_4, x2 = 0 [cpu4] Pass: msr s2_0_c0_c5_5, x2 = 0 (OK) (s2_0_c0_c5_5) [cpu4] Pass: msr s2_0_c0_c5_4, x2 = 0 (OK) (s2_0_c0_c5_4) [cpu4] Shadow: msr DBGWCR15_EL1, x2 = 0 [cpu4] Shadow: msr DBGWVR15_EL1, x2 = 0 [cpu4] Shadow: msr s2_0_c0_c1_7, x2 = 0 [cpu4] Shadow: msr s2_0_c0_c1_6, x2 = 0 [cpu4] Shadow: msr s2_0_c0_c2_7, x2 = 0 [cpu4] Shadow: msr s2_0_c0_c2_6, x2 = 0 [cpu4] Shadow: msr s2_0_c0_c3_7, x2 = 0 [cpu4] Shadow: msr s2_0_c0_c3_6, x2 = 0 [cpu5] Shadow: msr DBGBCR15_EL1, x2 = 0 [cpu5] Shadow: msr DBGBVR15_EL1, x2 = 0 [cpu5] Shadow: msr s2_0_c0_c1_5, x2 = 0 [cpu5] Shadow: msr s2_0_c0_c1_4, x2 = 0 [cpu5] Shadow: msr s2_0_c0_c2_5, x2 = 0 [cpu5] Shadow: msr s2_0_c0_c2_4, x2 = 0 [cpu5] Shadow: msr s2_0_c0_c3_5, x2 = 0 [cpu5] Shadow: msr s2_0_c0_c3_4, x2 = 0 [cpu5] Shadow: msr s2_0_c0_c4_5, x2 = 0 [cpu5] Shadow: msr s2_0_c0_c4_4, x2 = 0 [cpu5] Pass: msr s2_0_c0_c5_5, x2 = 0 (OK) (s2_0_c0_c5_5) [cpu5] Pass: msr s2_0_c0_c5_4, x2 = 0 (OK) (s2_0_c0_c5_4) [cpu5] Shadow: msr DBGWCR15_EL1, x2 = 0 [cpu5] Shadow: msr DBGWVR15_EL1, x2 = 0 [cpu5] Shadow: msr s2_0_c0_c1_7, x2 = 0 [cpu5] Shadow: msr s2_0_c0_c1_6, x2 = 0 [cpu5] Shadow: msr s2_0_c0_c2_7, x2 = 0 [cpu5] Shadow: msr s2_0_c0_c2_6, x2 = 0 [cpu5] Shadow: msr s2_0_c0_c3_7, x2 = 0 [cpu5] Shadow: msr s2_0_c0_c3_6, x2 = 0 [cpu6] Shadow: msr DBGBCR15_EL1, x2 = 0 [cpu6] Shadow: msr DBGBVR15_EL1, x2 = 0 [cpu6] Shadow: msr s2_0_c0_c1_5, x2 = 0 [cpu6] Shadow: msr s2_0_c0_c1_4, x2 = 0 [cpu6] Shadow: msr s2_0_c0_c2_5, x2 = 0 [cpu6] Shadow: msr s2_0_c0_c2_4, x2 = 0 [cpu6] Shadow: msr s2_0_c0_c3_5, x2 = 0 [cpu6] Shadow: msr s2_0_c0_c3_4, x2 = 0 [cpu6] Shadow: msr s2_0_c0_c4_5, x2 = 0 [cpu6] Shadow: msr s2_0_c0_c4_4, x2 = 0 [cpu6] Pass: msr s2_0_c0_c5_5, x2 = 0 (OK) (s2_0_c0_c5_5) [cpu6] Pass: msr s2_0_c0_c5_4, x2 = 0 (OK) (s2_0_c0_c5_4) [cpu6] Shadow: msr DBGWCR15_EL1, x2 = 0 [cpu6] Shadow: msr DBGWVR15_EL1, x2 = 0 [cpu6] Shadow: msr s2_0_c0_c1_7, x2 = 0 [cpu6] Shadow: msr s2_0_c0_c1_6, x2 = 0 [cpu6] Shadow: msr s2_0_c0_c2_7, x2 = 0 [cpu6] Shadow: msr s2_0_c0_c2_6, x2 = 0 [cpu6] Shadow: msr s2_0_c0_c3_7, x2 = 0 [cpu6] Shadow: msr s2_0_c0_c3_6, x2 = 0 [cpu7] Shadow: msr DBGBCR15_EL1, x2 = 0 [cpu7] Shadow: msr DBGBVR15_EL1, x2 = 0 [cpu7] Shadow: msr s2_0_c0_c1_5, x2 = 0 [cpu7] Shadow: msr s2_0_c0_c1_4, x2 = 0 [cpu7] Shadow: msr s2_0_c0_c2_5, x2 = 0 [cpu7] Shadow: msr s2_0_c0_c2_4, x2 = 0 [cpu7] Shadow: msr s2_0_c0_c3_5, x2 = 0 [cpu7] Shadow: msr s2_0_c0_c3_4, x2 = 0 [cpu7] Shadow: msr s2_0_c0_c4_5, x2 = 0 [cpu7] Shadow: msr s2_0_c0_c4_4, x2 = 0 [cpu7] Pass: msr s2_0_c0_c5_5, x2 = 0 (OK) (s2_0_c0_c5_5) [cpu7] Pass: msr s2_0_c0_c5_4, x2 = 0 (OK) (s2_0_c0_c5_4) [cpu7] Shadow: msr DBGWCR15_EL1, x2 = 0 [cpu7] Shadow: msr DBGWVR15_EL1, x2 = 0 [cpu7] Shadow: msr s2_0_c0_c1_7, x2 = 0 [cpu7] Shadow: msr s2_0_c0_c1_6, x2 = 0 [cpu7] Shadow: msr s2_0_c0_c2_7, x2 = 0 [cpu7] Shadow: msr s2_0_c0_c2_6, x2 = 0 [cpu7] Shadow: msr s2_0_c0_c3_7, x2 = 0 [cpu7] Shadow: msr s2_0_c0_c3_6, x2 = 0 [cpu8] Shadow: msr DBGBCR15_EL1, x2 = 0 [cpu8] Shadow: msr DBGBVR15_EL1, x2 = 0 [cpu8] Shadow: msr s2_0_c0_c1_5, x2 = 0 [cpu8] Shadow: msr s2_0_c0_c1_4, x2 = 0 [cpu8] Shadow: msr s2_0_c0_c2_5, x2 = 0 [cpu8] Shadow: msr s2_0_c0_c2_4, x2 = 0 [cpu8] Shadow: msr s2_0_c0_c3_5, x2 = 0 [cpu8] Shadow: msr s2_0_c0_c3_4, x2 = 0 [cpu8] Shadow: msr s2_0_c0_c4_5, x2 = 0 [cpu8] Shadow: msr s2_0_c0_c4_4, x2 = 0 [cpu8] Pass: msr s2_0_c0_c5_5, x2 = 0 (OK) (s2_0_c0_c5_5) [cpu8] Pass: msr s2_0_c0_c5_4, x2 = 0 (OK) (s2_0_c0_c5_4) [cpu8] Shadow: msr DBGWCR15_EL1, x2 = 0 [cpu8] Shadow: msr DBGWVR15_EL1, x2 = 0 [cpu8] Shadow: msr s2_0_c0_c1_7, x2 = 0 [cpu8] Shadow: msr s2_0_c0_c1_6, x2 = 0 [cpu8] Shadow: msr s2_0_c0_c2_7, x2 = 0 [cpu8] Shadow: msr s2_0_c0_c2_6, x2 = 0 [cpu8] Shadow: msr s2_0_c0_c3_7, x2 = 0 [cpu8] Shadow: msr s2_0_c0_c3_6, x2 = 0 [cpu9] Shadow: msr DBGBCR15_EL1, x2 = 0 [cpu9] Shadow: msr DBGBVR15_EL1, x2 = 0 [cpu9] Shadow: msr s2_0_c0_c1_5, x2 = 0 [cpu9] Shadow: msr s2_0_c0_c1_4, x2 = 0 [cpu9] Shadow: msr s2_0_c0_c2_5, x2 = 0 [cpu9] Shadow: msr s2_0_c0_c2_4, x2 = 0 [cpu9] Shadow: msr s2_0_c0_c3_5, x2 = 0 [cpu9] Shadow: msr s2_0_c0_c3_4, x2 = 0 [cpu9] Shadow: msr s2_0_c0_c4_5, x2 = 0 [cpu9] Shadow: msr s2_0_c0_c4_4, x2 = 0 [cpu9] Pass: msr s2_0_c0_c5_5, x2 = 0 (OK) (s2_0_c0_c5_5) [cpu9] Pass: msr s2_0_c0_c5_4, x2 = 0 (OK) (s2_0_c0_c5_4) [cpu9] Shadow: msr DBGWCR15_EL1, x2 = 0 [cpu9] Shadow: msr DBGWVR15_EL1, x2 = 0 [cpu9] Shadow: msr s2_0_c0_c1_7, x2 = 0 [cpu9] Shadow: msr s2_0_c0_c1_6, x2 = 0 [cpu9] Shadow: msr s2_0_c0_c2_7, x2 = 0 [cpu9] Shadow: msr s2_0_c0_c2_6, x2 = 0 [cpu9] Shadow: msr s2_0_c0_c3_7, x2 = 0 [cpu9] Shadow: msr s2_0_c0_c3_6, x2 = 0 [cpu4] PMGR R 28e0801d8+0:32 = 0xf0000ff -> 0xf0000ff [cpu4] PMGR R 28e0801d8+0:32 = 0xf0000ff -> 0xf0000ff [cpu4] PMGR W 28e0801d8+0:32 = 0x1f0000ff: Dangerous write [cpu4] PMGR R 28e0801f0+0:32 = 0xf0000ff -> 0xf0000ff [cpu4] PMGR R 28e0801f0+0:32 = 0xf0000ff -> 0xf0000ff [cpu4] PMGR W 28e0801f0+0:32 = 0x1f0000ff: Dangerous write [cpu4] PMGR R 28e080200+0:32 = 0xf0000ff -> 0xf0000ff [cpu4] PMGR R 28e080200+0:32 = 0xf0000ff -> 0xf0000ff [cpu4] PMGR W 28e080200+0:32 = 0x1f0000ff: Dangerous write [cpu4] PMGR R 28e080218+0:32 = 0xf0000ff -> 0xf0000ff [cpu4] PMGR R 28e080218+0:32 = 0xf0000ff -> 0xf0000ff [cpu4] PMGR W 28e080218+0:32 = 0x1f0000ff: Dangerous write [cpu4] PMGR R 28e080238+0:32 = 0xff -> 0xff [cpu4] PMGR R 28e080238+0:32 = 0xff -> 0xff [cpu4] PMGR W 28e080238+0:32 = 0x100000ff: Dangerous write [cpu4] PMGR R 28e580148+0:32 = 0xf0000ff -> 0xf0000ff [cpu4] PMGR R 28e580148+0:32 = 0xf0000ff -> 0xf0000ff [cpu4] PMGR W 28e580148+0:32 = 0x1f0000ff: Dangerous write [cpu4] PMGR R 28e580150+0:32 = 0xf0000ff -> 0xf0000ff [cpu4] PMGR R 28e580150+0:32 = 0xf0000ff -> 0xf0000ff [cpu4] PMGR W 28e580150+0:32 = 0x1f0000ff: Dangerous write [cpu4] PMGR R 28e580160+0:32 = 0xf0000ff -> 0xf0000ff [cpu4] PMGR R 28e580160+0:32 = 0xf0000ff -> 0xf0000ff [cpu4] PMGR W 28e580160+0:32 = 0x1f0000ff: Dangerous write [cpu4] PMGR R 28e580180+0:32 = 0xf0000ff -> 0xf0000ff [cpu4] PMGR R 28e580180+0:32 = 0xf0000ff -> 0xf0000ff [cpu4] PMGR W 28e580180+0:32 = 0x1f0000ff: Dangerous write [cpu4] PMGR R 28e580230+0:32 = 0xff -> 0xff [cpu4] PMGR R 28e580230+0:32 = 0xff -> 0xff [cpu4] PMGR W 28e580230+0:32 = 0x100000ff: Dangerous write [cpu4] PMGR R 28e580240+0:32 = 0xff -> 0xff [cpu4] PMGR R 28e580240+0:32 = 0xff -> 0xff [cpu4] PMGR W 28e580240+0:32 = 0x100000ff: Dangerous write [cpu4] PMGR R 292280088+0:32 = 0xff -> 0xff [cpu4] PMGR R 292280088+0:32 = 0xff -> 0xff [cpu4] PMGR W 292280088+0:32 = 0x100000ff: Dangerous write [cpu4] PMGR R 2922800d0+0:32 = 0xff -> 0xff [cpu4] PMGR R 2922800d0+0:32 = 0xff -> 0xff [cpu4] PMGR W 2922800d0+0:32 = 0x100000ff: Dangerous write [cpu7] PMGR R 2922800d0+0:32 = 0xff -> 0x100000ff [cpu7] PMGR W 2922800d0+0:32 = 0xf0: Dangerous write [cpu7] PMGR R 2922800d0+0:32 = 0xff -> 0x0 [cpu6] [0xffffb5fc07276464] MMIO: R.4 0x3860e8000 (isp0[0], offset 0x20e8000) = 0x1eff1020 [cpu6] [0xffffb5fc07276480] MMIO: R.4 0x3860e8004 (isp0[0], offset 0x20e8004) = 0x21037 [cpu6] [0xffffb5fc07276674] MMIO: R.4 0x3860e8060 (isp0[0], offset 0x20e8060) = 0xec006100 [cpu6] [0xffffb5fc07274820] MMIO: W.4 0x3860e8100 (isp0[0], offset 0x20e8100) = 0x0 [cpu6] [0xffffb5fc07274820] MMIO: W.4 0x3860e8104 (isp0[0], offset 0x20e8104) = 0x0 [cpu6] [0xffffb5fc07274820] MMIO: W.4 0x3860e8108 (isp0[0], offset 0x20e8108) = 0x0 [cpu6] [0xffffb5fc07274820] MMIO: W.4 0x3860e810c (isp0[0], offset 0x20e810c) = 0x0 [cpu6] [0xffffb5fc07274820] MMIO: W.4 0x3860e8110 (isp0[0], offset 0x20e8110) = 0x0 [cpu6] [0xffffb5fc07274820] MMIO: W.4 0x3860e8114 (isp0[0], offset 0x20e8114) = 0x0 [cpu6] [0xffffb5fc07274820] MMIO: W.4 0x3860e8118 (isp0[0], offset 0x20e8118) = 0x0 [cpu6] [0xffffb5fc07274820] MMIO: W.4 0x3860e811c (isp0[0], offset 0x20e811c) = 0x0 [cpu6] [0xffffb5fc07274820] MMIO: W.4 0x3860e8120 (isp0[0], offset 0x20e8120) = 0x0 [cpu6] [0xffffb5fc07274820] MMIO: W.4 0x3860e8124 (isp0[0], offset 0x20e8124) = 0x0 [cpu6] [0xffffb5fc07274820] MMIO: W.4 0x3860e8128 (isp0[0], offset 0x20e8128) = 0x0 [cpu6] [0xffffb5fc07274820] MMIO: W.4 0x3860e812c (isp0[0], offset 0x20e812c) = 0x0 [cpu6] [0xffffb5fc07274820] MMIO: W.4 0x3860e8130 (isp0[0], offset 0x20e8130) = 0x0 [cpu6] [0xffffb5fc07274820] MMIO: W.4 0x3860e8134 (isp0[0], offset 0x20e8134) = 0x0 [cpu6] [0xffffb5fc07274820] MMIO: W.4 0x3860e8138 (isp0[0], offset 0x20e8138) = 0x0 [cpu6] [0xffffb5fc07274820] MMIO: W.4 0x3860e813c (isp0[0], offset 0x20e813c) = 0x0 [cpu6] [0xffffb5fc072748c4] MMIO: W.4 0x3860e8200 (isp0[0], offset 0x20e8200) = 0x0 [cpu6] [0xffffb5fc072748c4] MMIO: W.4 0x3860e8210 (isp0[0], offset 0x20e8210) = 0x0 [cpu6] [0xffffb5fc072748c4] MMIO: W.4 0x3860e8220 (isp0[0], offset 0x20e8220) = 0x0 [cpu6] [0xffffb5fc072748c4] MMIO: W.4 0x3860e8230 (isp0[0], offset 0x20e8230) = 0x0 [cpu6] [0xffffb5fc072748c4] MMIO: W.4 0x3860e8240 (isp0[0], offset 0x20e8240) = 0x0 [cpu6] [0xffffb5fc072748c4] MMIO: W.4 0x3860e8250 (isp0[0], offset 0x20e8250) = 0x0 [cpu6] [0xffffb5fc072748c4] MMIO: W.4 0x3860e8260 (isp0[0], offset 0x20e8260) = 0x0 [cpu6] [0xffffb5fc072748c4] MMIO: W.4 0x3860e8270 (isp0[0], offset 0x20e8270) = 0x0 [cpu6] [0xffffb5fc072748c4] MMIO: W.4 0x3860e8280 (isp0[0], offset 0x20e8280) = 0x0 [cpu6] [0xffffb5fc072748c4] MMIO: W.4 0x3860e8290 (isp0[0], offset 0x20e8290) = 0x0 [cpu6] [0xffffb5fc072748c4] MMIO: W.4 0x3860e82a0 (isp0[0], offset 0x20e82a0) = 0x0 [cpu6] [0xffffb5fc072748c4] MMIO: W.4 0x3860e82b0 (isp0[0], offset 0x20e82b0) = 0x0 [cpu6] [0xffffb5fc072748c4] MMIO: W.4 0x3860e82c0 (isp0[0], offset 0x20e82c0) = 0x0 [cpu6] [0xffffb5fc072748c4] MMIO: W.4 0x3860e82d0 (isp0[0], offset 0x20e82d0) = 0x0 [cpu6] [0xffffb5fc072748c4] MMIO: W.4 0x3860e82e0 (isp0[0], offset 0x20e82e0) = 0x0 [cpu6] [0xffffb5fc072748c4] MMIO: W.4 0x3860e82f0 (isp0[0], offset 0x20e82f0) = 0x0 [cpu6] [0xffffb5fc072748c4] MMIO: W.4 0x3860e8204 (isp0[0], offset 0x20e8204) = 0x0 [cpu6] [0xffffb5fc072748c4] MMIO: W.4 0x3860e8214 (isp0[0], offset 0x20e8214) = 0x0 [cpu6] [0xffffb5fc072748c4] MMIO: W.4 0x3860e8224 (isp0[0], offset 0x20e8224) = 0x0 [cpu6] [0xffffb5fc072748c4] MMIO: W.4 0x3860e8234 (isp0[0], offset 0x20e8234) = 0x0 [cpu6] [0xffffb5fc072748c4] MMIO: W.4 0x3860e8244 (isp0[0], offset 0x20e8244) = 0x0 [cpu6] [0xffffb5fc072748c4] MMIO: W.4 0x3860e8254 (isp0[0], offset 0x20e8254) = 0x0 [cpu6] [0xffffb5fc072748c4] MMIO: W.4 0x3860e8264 (isp0[0], offset 0x20e8264) = 0x0 [cpu6] [0xffffb5fc072748c4] MMIO: W.4 0x3860e8274 (isp0[0], offset 0x20e8274) = 0x0 [cpu6] [0xffffb5fc072748c4] MMIO: W.4 0x3860e8284 (isp0[0], offset 0x20e8284) = 0x0 [cpu6] [0xffffb5fc072748c4] MMIO: W.4 0x3860e8294 (isp0[0], offset 0x20e8294) = 0x0 [cpu6] [0xffffb5fc072748c4] MMIO: W.4 0x3860e82a4 (isp0[0], offset 0x20e82a4) = 0x0 [cpu6] [0xffffb5fc072748c4] MMIO: W.4 0x3860e82b4 (isp0[0], offset 0x20e82b4) = 0x0 [cpu6] [0xffffb5fc072748c4] MMIO: W.4 0x3860e82c4 (isp0[0], offset 0x20e82c4) = 0x0 [cpu6] [0xffffb5fc072748c4] MMIO: W.4 0x3860e82d4 (isp0[0], offset 0x20e82d4) = 0x0 [cpu6] [0xffffb5fc072748c4] MMIO: W.4 0x3860e82e4 (isp0[0], offset 0x20e82e4) = 0x0 [cpu6] [0xffffb5fc072748c4] MMIO: W.4 0x3860e82f4 (isp0[0], offset 0x20e82f4) = 0x0 [cpu6] [0xffffb5fc072748c4] MMIO: W.4 0x3860e8208 (isp0[0], offset 0x20e8208) = 0x0 [cpu6] [0xffffb5fc072748c4] MMIO: W.4 0x3860e8218 (isp0[0], offset 0x20e8218) = 0x0 [cpu6] [0xffffb5fc072748c4] MMIO: W.4 0x3860e8228 (isp0[0], offset 0x20e8228) = 0x0 [cpu6] [0xffffb5fc072748c4] MMIO: W.4 0x3860e8238 (isp0[0], offset 0x20e8238) = 0x0 [cpu6] [0xffffb5fc072748c4] MMIO: W.4 0x3860e8248 (isp0[0], offset 0x20e8248) = 0x0 [cpu6] [0xffffb5fc072748c4] MMIO: W.4 0x3860e8258 (isp0[0], offset 0x20e8258) = 0x0 [cpu6] [0xffffb5fc072748c4] MMIO: W.4 0x3860e8268 (isp0[0], offset 0x20e8268) = 0x0 [cpu6] [0xffffb5fc072748c4] MMIO: W.4 0x3860e8278 (isp0[0], offset 0x20e8278) = 0x0 [cpu6] [0xffffb5fc072748c4] MMIO: W.4 0x3860e8288 (isp0[0], offset 0x20e8288) = 0x0 [cpu6] [0xffffb5fc072748c4] MMIO: W.4 0x3860e8298 (isp0[0], offset 0x20e8298) = 0x0 [cpu6] [0xffffb5fc072748c4] MMIO: W.4 0x3860e82a8 (isp0[0], offset 0x20e82a8) = 0x0 [cpu6] [0xffffb5fc072748c4] MMIO: W.4 0x3860e82b8 (isp0[0], offset 0x20e82b8) = 0x0 [cpu6] [0xffffb5fc072748c4] MMIO: W.4 0x3860e82c8 (isp0[0], offset 0x20e82c8) = 0x0 [cpu6] [0xffffb5fc072748c4] MMIO: W.4 0x3860e82d8 (isp0[0], offset 0x20e82d8) = 0x0 [cpu6] [0xffffb5fc072748c4] MMIO: W.4 0x3860e82e8 (isp0[0], offset 0x20e82e8) = 0x0 [cpu6] [0xffffb5fc072748c4] MMIO: W.4 0x3860e82f8 (isp0[0], offset 0x20e82f8) = 0x0 [cpu6] [0xffffb5fc072748c4] MMIO: W.4 0x3860e820c (isp0[0], offset 0x20e820c) = 0x0 [cpu6] [0xffffb5fc072748c4] MMIO: W.4 0x3860e821c (isp0[0], offset 0x20e821c) = 0x0 [cpu6] [0xffffb5fc072748c4] MMIO: W.4 0x3860e822c (isp0[0], offset 0x20e822c) = 0x0 [cpu6] [0xffffb5fc072748c4] MMIO: W.4 0x3860e823c (isp0[0], offset 0x20e823c) = 0x0 [cpu6] [0xffffb5fc072748c4] MMIO: W.4 0x3860e824c (isp0[0], offset 0x20e824c) = 0x0 [cpu6] [0xffffb5fc072748c4] MMIO: W.4 0x3860e825c (isp0[0], offset 0x20e825c) = 0x0 [cpu6] [0xffffb5fc072748c4] MMIO: W.4 0x3860e826c (isp0[0], offset 0x20e826c) = 0x0 [cpu6] [0xffffb5fc072748c4] MMIO: W.4 0x3860e827c (isp0[0], offset 0x20e827c) = 0x0 [cpu6] [0xffffb5fc072748c4] MMIO: W.4 0x3860e828c (isp0[0], offset 0x20e828c) = 0x0 [cpu6] [0xffffb5fc072748c4] MMIO: W.4 0x3860e829c (isp0[0], offset 0x20e829c) = 0x0 [cpu6] [0xffffb5fc072748c4] MMIO: W.4 0x3860e82ac (isp0[0], offset 0x20e82ac) = 0x0 [cpu6] [0xffffb5fc072748c4] MMIO: W.4 0x3860e82bc (isp0[0], offset 0x20e82bc) = 0x0 [cpu6] [0xffffb5fc072748c4] MMIO: W.4 0x3860e82cc (isp0[0], offset 0x20e82cc) = 0x0 [cpu6] [0xffffb5fc072748c4] MMIO: W.4 0x3860e82dc (isp0[0], offset 0x20e82dc) = 0x0 [cpu6] [0xffffb5fc072748c4] MMIO: W.4 0x3860e82ec (isp0[0], offset 0x20e82ec) = 0x0 [cpu6] [0xffffb5fc072748c4] MMIO: W.4 0x3860e82fc (isp0[0], offset 0x20e82fc) = 0x0 [cpu6] [0xffffb5fc0727596c] MMIO: W.4 0x3860e80fc (isp0[0], offset 0x20e80fc) = 0xffffffff [cpu6] [0xffffb5fc07275998] MMIO: R.4 0x3860e8040 (isp0[0], offset 0x20e8040) = 0xb000400 [cpu6] [0xffffb5fc072759bc] MMIO: W.4 0x3860e8040 (isp0[0], offset 0x20e8040) = 0xb000400 [cpu6] [0xffffb5fc072757b4] MMIO: W.4 0x3860e8034 (isp0[0], offset 0x20e8034) = 0xffff [cpu6] [0xffffb5fc072757cc] MMIO: W.4 0x3860e8020 (isp0[0], offset 0x20e8020) = 0x100000 [cpu6] [0xffffb5fc072757e8] MMIO: R.4 0x3860e8020 (isp0[0], offset 0x20e8020) = 0x100000 [cpu6] [0xffffb5fc07274e48] MMIO: R.4 0x3860e8100 (isp0[0], offset 0x20e8100) = 0x0 [cpu6] [0xffffb5fc07274e70] MMIO: R.4 0x3860e8200 (isp0[0], offset 0x20e8200) = 0x0 [cpu6] [0xffffb5fc07274e70] MMIO: R.4 0x3860e8204 (isp0[0], offset 0x20e8204) = 0x0 [cpu6] [0xffffb5fc07274e70] MMIO: R.4 0x3860e8208 (isp0[0], offset 0x20e8208) = 0x0 [cpu6] [0xffffb5fc07274e70] MMIO: R.4 0x3860e820c (isp0[0], offset 0x20e820c) = 0x0 [cpu6] [0xffffb5fc07274e48] MMIO: R.4 0x3860e8104 (isp0[0], offset 0x20e8104) = 0x0 [cpu6] [0xffffb5fc07274e70] MMIO: R.4 0x3860e8210 (isp0[0], offset 0x20e8210) = 0x0 [cpu6] [0xffffb5fc07274e70] MMIO: R.4 0x3860e8214 (isp0[0], offset 0x20e8214) = 0x0 [cpu6] [0xffffb5fc07274e70] MMIO: R.4 0x3860e8218 (isp0[0], offset 0x20e8218) = 0x0 [cpu6] [0xffffb5fc07274e70] MMIO: R.4 0x3860e821c (isp0[0], offset 0x20e821c) = 0x0 [cpu6] [0xffffb5fc07274e48] MMIO: R.4 0x3860e8108 (isp0[0], offset 0x20e8108) = 0x0 [cpu6] [0xffffb5fc07274e70] MMIO: R.4 0x3860e8220 (isp0[0], offset 0x20e8220) = 0x0 [cpu6] [0xffffb5fc07274e70] MMIO: R.4 0x3860e8224 (isp0[0], offset 0x20e8224) = 0x0 [cpu6] [0xffffb5fc07274e70] MMIO: R.4 0x3860e8228 (isp0[0], offset 0x20e8228) = 0x0 [cpu6] [0xffffb5fc07274e70] MMIO: R.4 0x3860e822c (isp0[0], offset 0x20e822c) = 0x0 [cpu6] [0xffffb5fc07274e48] MMIO: R.4 0x3860e810c (isp0[0], offset 0x20e810c) = 0x0 [cpu6] [0xffffb5fc07274e70] MMIO: R.4 0x3860e8230 (isp0[0], offset 0x20e8230) = 0x0 [cpu6] [0xffffb5fc07274e70] MMIO: R.4 0x3860e8234 (isp0[0], offset 0x20e8234) = 0x0 [cpu6] [0xffffb5fc07274e70] MMIO: R.4 0x3860e8238 (isp0[0], offset 0x20e8238) = 0x0 [cpu6] [0xffffb5fc07274e70] MMIO: R.4 0x3860e823c (isp0[0], offset 0x20e823c) = 0x0 [cpu6] [0xffffb5fc07274e48] MMIO: R.4 0x3860e8110 (isp0[0], offset 0x20e8110) = 0x0 [cpu6] [0xffffb5fc07274e70] MMIO: R.4 0x3860e8240 (isp0[0], offset 0x20e8240) = 0x0 [cpu6] [0xffffb5fc07274e70] MMIO: R.4 0x3860e8244 (isp0[0], offset 0x20e8244) = 0x0 [cpu6] [0xffffb5fc07274e70] MMIO: R.4 0x3860e8248 (isp0[0], offset 0x20e8248) = 0x0 [cpu6] [0xffffb5fc07274e70] MMIO: R.4 0x3860e824c (isp0[0], offset 0x20e824c) = 0x0 [cpu6] [0xffffb5fc07274e48] MMIO: R.4 0x3860e8114 (isp0[0], offset 0x20e8114) = 0x0 [cpu6] [0xffffb5fc07274e70] MMIO: R.4 0x3860e8250 (isp0[0], offset 0x20e8250) = 0x0 [cpu6] [0xffffb5fc07274e70] MMIO: R.4 0x3860e8254 (isp0[0], offset 0x20e8254) = 0x0 [cpu6] [0xffffb5fc07274e70] MMIO: R.4 0x3860e8258 (isp0[0], offset 0x20e8258) = 0x0 [cpu6] [0xffffb5fc07274e70] MMIO: R.4 0x3860e825c (isp0[0], offset 0x20e825c) = 0x0 [cpu6] [0xffffb5fc07274e48] MMIO: R.4 0x3860e8118 (isp0[0], offset 0x20e8118) = 0x0 [cpu6] [0xffffb5fc07274e70] MMIO: R.4 0x3860e8260 (isp0[0], offset 0x20e8260) = 0x0 [cpu6] [0xffffb5fc07274e70] MMIO: R.4 0x3860e8264 (isp0[0], offset 0x20e8264) = 0x0 [cpu6] [0xffffb5fc07274e70] MMIO: R.4 0x3860e8268 (isp0[0], offset 0x20e8268) = 0x0 [cpu6] [0xffffb5fc07274e70] MMIO: R.4 0x3860e826c (isp0[0], offset 0x20e826c) = 0x0 [cpu6] [0xffffb5fc07274e48] MMIO: R.4 0x3860e811c (isp0[0], offset 0x20e811c) = 0x0 [cpu6] [0xffffb5fc07274e70] MMIO: R.4 0x3860e8270 (isp0[0], offset 0x20e8270) = 0x0 [cpu6] [0xffffb5fc07274e70] MMIO: R.4 0x3860e8274 (isp0[0], offset 0x20e8274) = 0x0 [cpu6] [0xffffb5fc07274e70] MMIO: R.4 0x3860e8278 (isp0[0], offset 0x20e8278) = 0x0 [cpu6] [0xffffb5fc07274e70] MMIO: R.4 0x3860e827c (isp0[0], offset 0x20e827c) = 0x0 [cpu6] [0xffffb5fc07274e48] MMIO: R.4 0x3860e8120 (isp0[0], offset 0x20e8120) = 0x0 [cpu6] [0xffffb5fc07274e70] MMIO: R.4 0x3860e8280 (isp0[0], offset 0x20e8280) = 0x0 [cpu6] [0xffffb5fc07274e70] MMIO: R.4 0x3860e8284 (isp0[0], offset 0x20e8284) = 0x0 [cpu6] [0xffffb5fc07274e70] MMIO: R.4 0x3860e8288 (isp0[0], offset 0x20e8288) = 0x0 [cpu6] [0xffffb5fc07274e70] MMIO: R.4 0x3860e828c (isp0[0], offset 0x20e828c) = 0x0 [cpu6] [0xffffb5fc07274e48] MMIO: R.4 0x3860e8124 (isp0[0], offset 0x20e8124) = 0x0 [cpu6] [0xffffb5fc07274e70] MMIO: R.4 0x3860e8290 (isp0[0], offset 0x20e8290) = 0x0 [cpu6] [0xffffb5fc07274e70] MMIO: R.4 0x3860e8294 (isp0[0], offset 0x20e8294) = 0x0 [cpu6] [0xffffb5fc07274e70] MMIO: R.4 0x3860e8298 (isp0[0], offset 0x20e8298) = 0x0 [cpu6] [0xffffb5fc07274e70] MMIO: R.4 0x3860e829c (isp0[0], offset 0x20e829c) = 0x0 [cpu6] [0xffffb5fc07274e48] MMIO: R.4 0x3860e8128 (isp0[0], offset 0x20e8128) = 0x0 [cpu6] [0xffffb5fc07274e70] MMIO: R.4 0x3860e82a0 (isp0[0], offset 0x20e82a0) = 0x0 [cpu6] [0xffffb5fc07274e70] MMIO: R.4 0x3860e82a4 (isp0[0], offset 0x20e82a4) = 0x0 [cpu6] [0xffffb5fc07274e70] MMIO: R.4 0x3860e82a8 (isp0[0], offset 0x20e82a8) = 0x0 [cpu6] [0xffffb5fc07274e70] MMIO: R.4 0x3860e82ac (isp0[0], offset 0x20e82ac) = 0x0 [cpu6] [0xffffb5fc07274e48] MMIO: R.4 0x3860e812c (isp0[0], offset 0x20e812c) = 0x0 [cpu6] [0xffffb5fc07274e70] MMIO: R.4 0x3860e82b0 (isp0[0], offset 0x20e82b0) = 0x0 [cpu6] [0xffffb5fc07274e70] MMIO: R.4 0x3860e82b4 (isp0[0], offset 0x20e82b4) = 0x0 [cpu6] [0xffffb5fc07274e70] MMIO: R.4 0x3860e82b8 (isp0[0], offset 0x20e82b8) = 0x0 [cpu6] [0xffffb5fc07274e70] MMIO: R.4 0x3860e82bc (isp0[0], offset 0x20e82bc) = 0x0 [cpu6] [0xffffb5fc07274e48] MMIO: R.4 0x3860e8130 (isp0[0], offset 0x20e8130) = 0x0 [cpu6] [0xffffb5fc07274e70] MMIO: R.4 0x3860e82c0 (isp0[0], offset 0x20e82c0) = 0x0 [cpu6] [0xffffb5fc07274e70] MMIO: R.4 0x3860e82c4 (isp0[0], offset 0x20e82c4) = 0x0 [cpu6] [0xffffb5fc07274e70] MMIO: R.4 0x3860e82c8 (isp0[0], offset 0x20e82c8) = 0x0 [cpu6] [0xffffb5fc07274e70] MMIO: R.4 0x3860e82cc (isp0[0], offset 0x20e82cc) = 0x0 [cpu6] [0xffffb5fc07274e48] MMIO: R.4 0x3860e8134 (isp0[0], offset 0x20e8134) = 0x0 [cpu6] [0xffffb5fc07274e70] MMIO: R.4 0x3860e82d0 (isp0[0], offset 0x20e82d0) = 0x0 [cpu6] [0xffffb5fc07274e70] MMIO: R.4 0x3860e82d4 (isp0[0], offset 0x20e82d4) = 0x0 [cpu6] [0xffffb5fc07274e70] MMIO: R.4 0x3860e82d8 (isp0[0], offset 0x20e82d8) = 0x0